Fixed todo's related to mul_en/div_en i EX stage #902

silabs-oysteink · 2023-08-08T12:40:31Z

Factored halt_ex/kill_ex out of mul_en and div_en - multiplier and divider now handles them theirselves.
In the divider, div_en_i and valid_i was then duplicates, changed to using only valid_i.

SEC clean (with multiplier operation converted to add to enable converging SEC)

… EX stage. Routing halt_ex and kill_ex into the multiplier and divider, making sure no state updates occur while halted and that the modules properly drive valid/ready according to halt/kill. SEC clean (multiplier operation was converted to addition to be able to complete SEC run) Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>

Silabs-ArjanB · 2023-08-14T10:41:22Z

rtl/cv32e40x_mult.sv

@@ -115,7 +118,7 @@ module cv32e40x_mult import cv32e40x_pkg::*;
    mulh_acc_next    = mulh_acc;

    // Case statement assumes valid_i = 1; the valid_i = 0 scenario
-    // is handled after the case statement.    
+    // is handled after the case statement.


Remove comment (no longer accurate)

Removed comment.

Comment seems still there

Silabs-ArjanB · 2023-08-14T10:42:04Z

rtl/cv32e40x_mult.sv


          if (ready_i) begin
-            ready_o        = 1'b1;
+            ready_o       = !halt_i || kill_i;


Normally we would set ready_o = 1 upon kill even if ready_i=0. Would that be SEC clean as well?

I will check :)

Updated, SEC clean.

Silabs-ArjanB · 2023-08-14T10:43:01Z

rtl/cv32e40x_mult.sv

        mulh_a            = mulh_ah;
        mulh_b            = mulh_bh;

        if (ready_i) begin
-          ready_o         = 1'b1;
+          ready_o         = !halt_i || kill_i;


Same remark here

Updated code, SEC clean.

Silabs-ArjanB · 2023-08-14T10:43:57Z

rtl/cv32e40x_mult.sv

          mulh_state_next = MUL_ALBL;
          mulh_acc_next   = '0;
        end
      end
      default: ;
    endcase

-    // Allow kill at any time
-    if (!valid_i) begin
+    // Allow kill at any time unless EX stage is halted


I don't understand the changed comment here

Me neither, I will revert it (likely remnants of another approach at using halt/kill in the multiplier)

Silabs-ArjanB · 2023-08-14T10:47:04Z

rtl/cv32e40x_mult.sv

@@ -177,8 +180,10 @@ module cv32e40x_mult import cv32e40x_pkg::*;
      mulh_acc   <=  '0;
      mulh_state <= MUL_ALBL;
    end else begin
-      mulh_acc   <= mulh_acc_next;
-      mulh_state <= mulh_state_next;
+      if ((valid_i && !halt_i) || kill_i) begin


Above mulh_state_next is changed also for !valid, but here that scenario is not handled

Fixed, SEC clean.

Silabs-ArjanB · 2023-08-14T10:51:47Z

rtl/cv32e40x_div.sv

        if (ready_i) begin
-          ready_o    = 1'b1;
+          ready_o    = !halt_i || kill_i;


Same remark as for multiplier

Fixed, SEC clean.

Silabs-ArjanB · 2023-08-14T10:52:30Z

rtl/cv32e40x_div.sv

@@ -304,6 +305,8 @@ module cv32e40x_div import cv32e40x_pkg::*;
       comp_inv_q  <= 1'b0;
       res_inv_q   <= 1'b0;
    end else begin
+      // If stage is halted, the divider should have no state updates
+      if ((valid_i && !halt_i) || kill_i) begin


Same remark as for multiplier

Fixed, SEC clean.

SEC clean. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>

Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>

Silabs-ArjanB · 2023-08-15T11:54:05Z

rtl/cv32e40x_div.sv

@@ -258,9 +259,9 @@ module cv32e40x_div import cv32e40x_pkg::*;
      end

      DIV_FINISH: begin
-        valid_o = 1'b1;
+        valid_o = valid_i && !(halt_i || kill_i); // No valid outputs while halted or killed
+        ready_o = (ready_i && !halt_i) || kill_i;


Now halt impacts ready_o but not next_state. I see that next-state is not used later on in that case, but it is just difficult to understand like this.

Maybe keep case statement as in original design and assume valid_i=1, halt_i=0, kill_i=0 within the case and deal with exceptions to that assumption after the case statement.

Reverted to original case statement.

Silabs-ArjanB · 2023-08-15T11:57:47Z

rtl/cv32e40x_mult.sv

@@ -115,7 +118,7 @@ module cv32e40x_mult import cv32e40x_pkg::*;
    mulh_acc_next    = mulh_acc;

    // Case statement assumes valid_i = 1; the valid_i = 0 scenario
-    // is handled after the case statement.    
+    // is handled after the case statement.


Comment seems still there

…fter/in parallell with the case. Clock gating flipflops when halted or when there are no valid inputs. SEC clean (with multiplier operation modified to addition) Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>

…eink/cv32e40x into silabs-oysteink-div-mul-todo

Silabs-ArjanB · 2023-08-25T07:40:12Z

rtl/cv32e40x_mult.sv

+      mulh_b        = mulh_bl;
+    end else begin
+      if (halt_i) begin
+        valid_o = 1'b0;


mulh_state_next assignment missing

Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>

silabs-oysteink added the Component:RTL For issues in the RTL (e.g. for files in the rtl directory) label Aug 8, 2023

silabs-oysteink requested a review from Silabs-ArjanB August 8, 2023 12:40

Silabs-ArjanB requested changes Aug 14, 2023

View reviewed changes

Updates after review.

d08568d

SEC clean. Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>

silabs-oysteink requested a review from Silabs-ArjanB August 14, 2023 13:12

silabs-oysteink and others added 2 commits August 14, 2023 15:14

Comment update.

3a9f78b

Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>

Update cv32e40x_ex_stage.sv

4287cc3

Silabs-ArjanB requested changes Aug 15, 2023

View reviewed changes

silabs-oysteink added 2 commits August 17, 2023 13:10

Merge branch 'silabs-oysteink-div-mul-todo' of github.com:silabs-oyst…

6e0214e

…eink/cv32e40x into silabs-oysteink-div-mul-todo

silabs-oysteink requested a review from Silabs-ArjanB August 17, 2023 11:21

Silabs-ArjanB requested changes Aug 25, 2023

View reviewed changes

Review fixes.

ec7f6e7

Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>

silabs-oysteink requested a review from Silabs-ArjanB August 25, 2023 08:59

Silabs-ArjanB approved these changes Aug 25, 2023

View reviewed changes

Silabs-ArjanB merged commit d17c4e7 into openhwgroup:master Aug 25, 2023
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Fixed todo's related to mul_en/div_en i EX stage #902

Fixed todo's related to mul_en/div_en i EX stage #902

silabs-oysteink commented Aug 8, 2023

Silabs-ArjanB Aug 14, 2023

silabs-oysteink Aug 14, 2023

Silabs-ArjanB Aug 15, 2023

Silabs-ArjanB Aug 14, 2023

silabs-oysteink Aug 14, 2023

silabs-oysteink Aug 14, 2023

Silabs-ArjanB Aug 14, 2023

silabs-oysteink Aug 14, 2023

Silabs-ArjanB Aug 14, 2023

silabs-oysteink Aug 14, 2023

Silabs-ArjanB Aug 14, 2023

silabs-oysteink Aug 14, 2023

Silabs-ArjanB Aug 14, 2023

silabs-oysteink Aug 14, 2023

Silabs-ArjanB Aug 14, 2023

silabs-oysteink Aug 14, 2023

Silabs-ArjanB Aug 15, 2023

silabs-oysteink Aug 17, 2023

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Silabs-ArjanB Aug 25, 2023

silabs-oysteink Aug 25, 2023

Fixed todo's related to mul_en/div_en i EX stage #902

Fixed todo's related to mul_en/div_en i EX stage #902

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silabs-oysteink commented Aug 8, 2023

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