Fix for issue #586 #955
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Fix for issue #586 #955
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Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
silabs-oysteink
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Silabs-ArjanB
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Sep 25, 2023
| @@ -668,7 +668,7 @@ Detailed: | |||
| | 1:0 | WARL (0x0, 0x1) | **MODE**: Interrupt handling mode. 0x0 = non-vectored CLINT mode, 0x1 = vectored CLINT mode. | | |||
| +---------+------------------+---------------------------------------------------------------------------------------------------------------+ | |||
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| The initial value of ``mtvec`` is equal to {**mtvec_addr_i[31:7]**, 5'b0, 2'b01}. | |||
| Out of reset ``mtvec`` has the value of 32'h00000001. This value is not observable by SW as ``mtvec`` is initialized to {**mtvec_addr_i[31:7]**, 5'b0, 2'b01} when ``fetch_enable_i`` is asserted the first time after reset. | |||
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after reset -> after reset release
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Fixed already (?)
| @@ -710,7 +710,7 @@ Detailed: | |||
| | 1:0 | WARL (0x3) | **MODE**: Interrupt handling mode. Always CLIC mode. | | |||
| +---------+------------------+---------------------------------------------------------------------------------------------------------------+ | |||
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| The initial value of ``mtvec`` is equal to {**mtvec_addr_i[31:7]**, 1'b0, 6'b000011}. | |||
| Out of reset ``mtvec`` has the value of 32'h00000003. This value is not observable by SW as ``mtvec`` is initialized to {**mtvec_addr_i[31:7]**, 1'b0, 6'b00000011} when ``fetch_enable_i`` is asserted the first time after reset. | |||
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after reset -> after reset release
6'b00000011 -> 6'b000011
Signed-off-by: Oystein Knauserud <Oystein.Knauserud@silabs.com>
Silabs-ArjanB
approved these changes
Sep 25, 2023
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Updated description of mtvec reset and initialization.
Other CSR reset values seems clear to me, those with dependencies on various parameters or input values are described.