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Lint fixes. Don't use logical operators on multi-bit signals #968

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merged 1 commit into from Oct 11, 2023
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2 changes: 1 addition & 1 deletion rtl/cv32e40x_controller_bypass.sv
Expand Up @@ -206,7 +206,7 @@ module cv32e40x_controller_bypass import cv32e40x_pkg::*;
// deassert WE when the core has an exception in ID (ins converted to nop and propagated to WB)
// Also deassert for trigger match, as with dcsr.timing==0 we do not execute before entering debug mode
// CLIC pointer fetches go through the pipeline, but no write enables should be active.
if (if_id_pipe_i.instr.bus_resp.err || !(if_id_pipe_i.instr.mpu_status == MPU_OK) || if_id_pipe_i.trigger_match ||
if (if_id_pipe_i.instr.bus_resp.err || !(if_id_pipe_i.instr.mpu_status == MPU_OK) || (|if_id_pipe_i.trigger_match) ||
if_id_pipe_i.instr_meta.clic_ptr || if_id_pipe_i.instr_meta.mret_ptr) begin
ctrl_byp_o.deassert_we = 1'b1;
end
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2 changes: 1 addition & 1 deletion rtl/cv32e40x_controller_fsm.sv
Expand Up @@ -1331,7 +1331,7 @@ module cv32e40x_controller_fsm import cv32e40x_pkg::*;
// If debug entry is caused by a watchpoint address trigger, then abort_op_wb_i will be 1 and a debug entry is initiated.
// This must also cause the sequence_in_progress_wb to be reset as the sequence is effectively terminated, although the instruction itself is not killed or completed
// in a normal manner. As the WB stage is halted for debug entry on a watchcpoint trigger, wb_valid_i is zero.
if (ex_wb_pipe_i.instr_valid && wpt_match_wb_i && abort_op_wb_i) begin
if (ex_wb_pipe_i.instr_valid && (|wpt_match_wb_i) && abort_op_wb_i) begin
sequence_in_progress_wb <= 1'b0;
end
end
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