Define InstrTlbEntries, DataTlbEntries, cfg.NrLoadPipeRegs, NrStorePi…

…peRegs, DcacheIdWidth as CVA6 parameters (#2034)

core/cache_subsystem/cache_ctrl.sv

@@ -81,7 +81,7 @@ module cache_ctrl
   typedef struct packed {
     logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] index;
     logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0]   tag;
-    logic [DCACHE_TID_WIDTH-1:0]           id;
+    logic [CVA6Cfg.DcacheIdWidth-1:0]      id;
     logic [7:0]                            be;
     logic [1:0]                            size;
     logic                                  we;

core/cache_subsystem/wt_dcache.sv

@@ -191,7 +191,7 @@ module wt_dcache
   // 0 is used by MMU, 1 by READ access requests
   for (genvar k = 0; k < NumPorts - 1; k++) begin : gen_rd_ports
     // set these to high prio ports
-    if ((k == 0 && MMU_PRESENT) || (k == 1) || (k == 2 && CVA6Cfg.EnableAccelerator)) begin
+    if ((k == 0 && CVA6Cfg.MmuPresent) || (k == 1) || (k == 2 && CVA6Cfg.EnableAccelerator)) begin
       assign rd_prio[k] = 1'b1;
       wt_dcache_ctrl #(
           .CVA6Cfg(CVA6Cfg),

core/cache_subsystem/wt_dcache_ctrl.sv

@@ -73,7 +73,7 @@ module wt_dcache_ctrl
   logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] address_tag_d, address_tag_q;
   logic [DCACHE_CL_IDX_WIDTH-1:0] address_idx_d, address_idx_q;
   logic [CVA6Cfg.DCACHE_OFFSET_WIDTH-1:0] address_off_d, address_off_q;
-  logic [DCACHE_TID_WIDTH-1:0] id_d, id_q;
+  logic [CVA6Cfg.DcacheIdWidth-1:0] id_d, id_q;
   logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] vld_data_d, vld_data_q;
   logic save_tag, rd_req_d, rd_req_q, rd_ack_d, rd_ack_q;
   logic [1:0] data_size_d, data_size_q;

core/csr_regfile.sv

@@ -551,7 +551,7 @@ module csr_regfile
         riscv::CSR_MHARTID: csr_rdata = hart_id_i;
         riscv::CSR_MCONFIGPTR: csr_rdata = '0;  // not implemented
         riscv::CSR_MCOUNTINHIBIT:
-        if (PERF_COUNTER_EN)
+        if (CVA6Cfg.PerfCounterEn)
           csr_rdata = {{(CVA6Cfg.XLEN - (MHPMCounterNum + 3)) {1'b0}}, mcountinhibit_q};
         else read_access_exception = 1'b1;
         // Counters and Timers
@@ -806,12 +806,13 @@ module csr_regfile
     if (!debug_mode_q) begin
       // increase instruction retired counter
       for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
-        if (commit_ack_i[i] && !ex_i.valid && (!PERF_COUNTER_EN || (PERF_COUNTER_EN && !mcountinhibit_q[2])))
+        if (commit_ack_i[i] && !ex_i.valid && (!CVA6Cfg.PerfCounterEn || (CVA6Cfg.PerfCounterEn && !mcountinhibit_q[2])))
           instret++;
       end
       instret_d = instret;
       // increment the cycle count
-      if (!PERF_COUNTER_EN || (PERF_COUNTER_EN && !mcountinhibit_q[0])) cycle_d = cycle_q + 1'b1;
+      if (!CVA6Cfg.PerfCounterEn || (CVA6Cfg.PerfCounterEn && !mcountinhibit_q[0]))
+        cycle_d = cycle_q + 1'b1;
       else cycle_d = cycle_q;
     end
 
@@ -1366,7 +1367,8 @@ module csr_regfile
           if (!CVA6Cfg.RVU || CVA6Cfg.XLEN != 32) update_access_exception = 1'b1;
         end
         riscv::CSR_MCOUNTINHIBIT:
-        if (PERF_COUNTER_EN) mcountinhibit_d = {csr_wdata[MHPMCounterNum+2:2], 1'b0, csr_wdata[0]};
+        if (CVA6Cfg.PerfCounterEn)
+          mcountinhibit_d = {csr_wdata[MHPMCounterNum+2:2], 1'b0, csr_wdata[0]};
         else update_access_exception = 1'b1;
         // performance counters
         riscv::CSR_MCYCLE: cycle_d[CVA6Cfg.XLEN-1:0] = csr_wdata;
@@ -1884,7 +1886,7 @@ module csr_regfile
 
       en_ld_st_g_translation_o = (en_ld_st_g_translation_q && !csr_hs_ld_st_inst_i) || (csr_hs_ld_st_inst_i && config_pkg::vm_mode_t'(hgatp_q.mode) == CVA6Cfg.MODE_SV && csr_hs_ld_st_inst_i);
     end else begin
-      if (ariane_pkg::MMU_PRESENT && mprv && CVA6Cfg.RVS && config_pkg::vm_mode_t'(satp_q.mode) == CVA6Cfg.MODE_SV && (mstatus_q.mpp != riscv::PRIV_LVL_M))
+      if (CVA6Cfg.MmuPresent && mprv && CVA6Cfg.RVS && config_pkg::vm_mode_t'(satp_q.mode) == CVA6Cfg.MODE_SV && (mstatus_q.mpp != riscv::PRIV_LVL_M))
         en_ld_st_translation_d = 1'b1;
       else  // otherwise we go with the regular settings
         en_ld_st_translation_d = en_translation_o;

core/cva6.sv

@@ -191,15 +191,15 @@ module cva6
       logic                                  data_we;
       logic [(CVA6Cfg.XLEN/8)-1:0]           data_be;
       logic [1:0]                            data_size;
-      logic [DCACHE_TID_WIDTH-1:0]           data_id;
+      logic [CVA6Cfg.DcacheIdWidth-1:0]      data_id;
       logic                                  kill_req;
       logic                                  tag_valid;
     },
 
     localparam type dcache_req_o_t = struct packed {
       logic                                 data_gnt;
       logic                                 data_rvalid;
-      logic [DCACHE_TID_WIDTH-1:0]          data_rid;
+      logic [CVA6Cfg.DcacheIdWidth-1:0]     data_rid;
       logic [CVA6Cfg.XLEN-1:0]              data_rdata;
       logic [CVA6Cfg.DCACHE_USER_WIDTH-1:0] data_ruser;
     },
@@ -1076,7 +1076,7 @@ module cva6
   // ------------------------
   // Performance Counters
   // ------------------------
-  if (PERF_COUNTER_EN) begin : gen_perf_counter
+  if (CVA6Cfg.PerfCounterEn) begin : gen_perf_counter
     perf_counters #(
         .CVA6Cfg(CVA6Cfg),
         .bp_resolve_t(bp_resolve_t),

core/frontend/frontend.sv

@@ -447,9 +447,9 @@ module frontend
         end
 
         // Map the only three exceptions which can occur in the frontend to a two bit enum
-        if (ariane_pkg::MMU_PRESENT && icache_dreq_i.ex.cause == riscv::INSTR_GUEST_PAGE_FAULT) begin
+        if (CVA6Cfg.MmuPresent && icache_dreq_i.ex.cause == riscv::INSTR_GUEST_PAGE_FAULT) begin
           icache_ex_valid_q <= ariane_pkg::FE_INSTR_GUEST_PAGE_FAULT;
-        end else if (ariane_pkg::MMU_PRESENT && icache_dreq_i.ex.cause == riscv::INSTR_PAGE_FAULT) begin
+        end else if (CVA6Cfg.MmuPresent && icache_dreq_i.ex.cause == riscv::INSTR_PAGE_FAULT) begin
           icache_ex_valid_q <= ariane_pkg::FE_INSTR_PAGE_FAULT;
         end else if (icache_dreq_i.ex.cause == riscv::INSTR_ACCESS_FAULT) begin
           icache_ex_valid_q <= ariane_pkg::FE_INSTR_ACCESS_FAULT;

core/frontend/instr_queue.sv

@@ -151,7 +151,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
 
   assign ready_o = ~(|instr_queue_full) & ~full_address;
 
-  if (ariane_pkg::RVC) begin : gen_multiple_instr_per_fetch_with_C
+  if (CVA6Cfg.RVC) begin : gen_multiple_instr_per_fetch_with_C
 
     for (genvar i = 0; i < CVA6Cfg.INSTR_PER_FETCH; i++) begin : gen_unpack_taken
       assign taken[i] = cf_type_i[i] != ariane_pkg::NoCF;
@@ -278,7 +278,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
   // (e.g.: we pushed and it was full)
   // 2. The address/branch predict FIFO was full
   // if one of the FIFOs was full we need to replay the faulting instruction
-  if (ariane_pkg::RVC == 1'b1) begin : gen_instr_overflow_fifo_with_C
+  if (CVA6Cfg.RVC == 1'b1) begin : gen_instr_overflow_fifo_with_C
     assign instr_overflow_fifo = instr_queue_full & fifo_pos;
   end else begin : gen_instr_overflow_fifo_without_C
     assign instr_overflow_fifo = instr_queue_full & valid_i;
@@ -287,7 +287,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
   assign address_overflow = full_address & push_address;
   assign replay_o = instr_overflow | address_overflow;
 
-  if (ariane_pkg::RVC) begin : gen_replay_addr_o_with_c
+  if (CVA6Cfg.RVC) begin : gen_replay_addr_o_with_c
     // select the address, in the case of an address fifo overflow just
     // use the base of this package
     // if we successfully pushed some instructions we can output the next instruction
@@ -318,7 +318,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
     end
   end
 
-  if (ariane_pkg::RVC) begin : gen_downstream_itf_with_c
+  if (CVA6Cfg.RVC) begin : gen_downstream_itf_with_c
     always_comb begin
       idx_ds_d  = idx_ds_q;
 
@@ -516,7 +516,7 @@ ariane_pkg::FETCH_FIFO_DEPTH
   unread i_unread_fifo_pos (.d_i(|fifo_pos_extended));  // we don't care about the lower signals
   unread i_unread_instr_fifo (.d_i(|instr_queue_usage));
 
-  if (ariane_pkg::RVC) begin : gen_pc_q_with_c
+  if (CVA6Cfg.RVC) begin : gen_pc_q_with_c
     always_ff @(posedge clk_i or negedge rst_ni) begin
       if (!rst_ni) begin
         idx_ds_q        <= 'b1;

core/include/ariane_pkg.sv

@@ -44,8 +44,6 @@ package ariane_pkg;
   // allocate more space for the commit buffer to be on the save side, this needs to be a power of two
   localparam logic [2:0] DEPTH_COMMIT = 'd4;
 
-  localparam bit RVC = cva6_config_pkg::CVA6ConfigCExtEn;  // Is C extension configuration
-
   // Transprecision float unit
   localparam int unsigned LAT_COMP_FP32 = 'd2;
   localparam int unsigned LAT_COMP_FP64 = 'd3;
@@ -261,8 +259,6 @@ package ariane_pkg;
   localparam int unsigned MEM_TID_WIDTH = `L15_THREADID_WIDTH;
 `endif
 
-  localparam int unsigned DCACHE_TID_WIDTH = cva6_config_pkg::CVA6ConfigDcacheIdWidth;
-
   localparam int unsigned WT_DCACHE_WBUF_DEPTH = cva6_config_pkg::CVA6ConfigWtDcacheWbufDepth;
 
   // ---------------
@@ -578,15 +574,12 @@ package ariane_pkg;
   // ---------------
   // MMU instanciation
   // ---------------
-  localparam bit MMU_PRESENT = cva6_config_pkg::CVA6ConfigMmuPresent;
-
   localparam int unsigned INSTR_TLB_ENTRIES = cva6_config_pkg::CVA6ConfigInstrTlbEntries;
   localparam int unsigned DATA_TLB_ENTRIES = cva6_config_pkg::CVA6ConfigDataTlbEntries;
 
   // -------------------
   // Performance counter
   // -------------------
-  localparam bit PERF_COUNTER_EN = cva6_config_pkg::CVA6ConfigPerfCounterEn;
   localparam int unsigned MHPMCounterNum = 6;
 
   // --------------------

core/include/build_config_pkg.sv

@@ -41,6 +41,8 @@ package build_config_pkg;
 
     cfg.FpgaEn = CVA6Cfg.FpgaEn;
     cfg.NrCommitPorts = CVA6Cfg.NrCommitPorts;
+    cfg.NrLoadPipeRegs = CVA6Cfg.NrLoadPipeRegs;
+    cfg.NrStorePipeRegs = CVA6Cfg.NrStorePipeRegs;
     cfg.AxiAddrWidth = CVA6Cfg.AxiAddrWidth;
     cfg.AxiDataWidth = CVA6Cfg.AxiDataWidth;
     cfg.AxiIdWidth = CVA6Cfg.AxiIdWidth;
@@ -76,6 +78,8 @@ package build_config_pkg;
     cfg.NrRgprPorts = unsigned'(2);
     cfg.NrWbPorts = unsigned'(NrWbPorts);
     cfg.EnableAccelerator = bit'(EnableAccelerator);
+    cfg.PerfCounterEn = CVA6Cfg.PerfCounterEn;
+    cfg.MmuPresent = CVA6Cfg.MmuPresent;
     cfg.RVS = CVA6Cfg.RVS;
     cfg.RVU = CVA6Cfg.RVU;
 
@@ -112,6 +116,7 @@ package build_config_pkg;
     cfg.ICACHE_LINE_WIDTH = CVA6Cfg.IcacheLineWidth;
     cfg.ICACHE_USER_LINE_WIDTH = (CVA6Cfg.AxiUserWidth == 1) ? 4 : CVA6Cfg.IcacheLineWidth;
     cfg.DCacheType = CVA6Cfg.DCacheType;
+    cfg.DcacheIdWidth = CVA6Cfg.DcacheIdWidth;
     cfg.DCACHE_SET_ASSOC = CVA6Cfg.DcacheSetAssoc;
     cfg.DCACHE_SET_ASSOC_WIDTH = $clog2(CVA6Cfg.DcacheSetAssoc);
     cfg.DCACHE_INDEX_WIDTH = DCACHE_INDEX_WIDTH;
@@ -142,6 +147,8 @@ package build_config_pkg;
     cfg.MODE_SV = (CVA6Cfg.XLEN == 32) ? config_pkg::ModeSv32 : config_pkg::ModeSv39;
     cfg.SV = (cfg.MODE_SV == config_pkg::ModeSv32) ? 32 : 39;
     cfg.SVX = (cfg.MODE_SV == config_pkg::ModeSv32) ? 34 : 41;
+    cfg.InstrTlbEntries = CVA6Cfg.InstrTlbEntries;
+    cfg.DataTlbEntries = CVA6Cfg.DataTlbEntries;
 
     return cfg;
   endfunction

core/include/config_pkg.sv

@@ -74,6 +74,10 @@ package config_pkg;
     bit                          XF8;
     // Non standard Vector Floating Point extension
     bit                          XFVec;
+    // Perf counters
+    bit                          PerfCounterEn;
+    // MMU
+    bit                          MmuPresent;
     // Supervisor mode
     bit                          RVS;
     // User mode
@@ -138,6 +142,8 @@ package config_pkg;
     int unsigned                 IcacheLineWidth;
     // Cache Type
     cache_type_t                 DCacheType;
+    // Data cache ID
+    int unsigned                 DcacheIdWidth;
     // Data cache size (in bytes)
     int unsigned                 DcacheByteSize;
     // Data cache associativity (number of ways)
@@ -154,6 +160,10 @@ package config_pkg;
     bit                          FpgaEn;
     // Number of commit ports
     int unsigned                 NrCommitPorts;
+    // Load cycle latency number
+    int unsigned                 NrLoadPipeRegs;
+    // Store cycle latency number
+    int unsigned                 NrStorePipeRegs;
     // Scoreboard length
     int unsigned                 NrScoreboardEntries;
     // Load buffer entry buffer
@@ -166,6 +176,10 @@ package config_pkg;
     int unsigned                 BTBEntries;
     // Branch history entries
     int unsigned                 BHTEntries;
+    // MMU instruction TLB entries
+    int unsigned                 InstrTlbEntries;
+    // MMU data TLB entries
+    int unsigned                 DataTlbEntries;
   } cva6_user_cfg_t;
 
   typedef struct packed {
@@ -185,6 +199,8 @@ package config_pkg;
     /// ports than issue ports, for the scoreboard to empty out in case one
     /// instruction stalls a little longer.
     int unsigned NrCommitPorts;
+    int unsigned NrLoadPipeRegs;
+    int unsigned NrStorePipeRegs;
     /// AXI parameters.
     int unsigned AxiAddrWidth;
     int unsigned AxiDataWidth;
@@ -222,14 +238,19 @@ package config_pkg;
     int unsigned NrRgprPorts;
     int unsigned NrWbPorts;
     bit          EnableAccelerator;
+    bit          PerfCounterEn;
+    bit          MmuPresent;
     bit          RVS;                //Supervisor mode
     bit          RVU;                //User mode
 
-    logic [63:0]                 HaltAddress;
-    logic [63:0]                 ExceptionAddress;
-    int unsigned                 RASDepth;
-    int unsigned                 BTBEntries;
-    int unsigned                 BHTEntries;
+    logic [63:0] HaltAddress;
+    logic [63:0] ExceptionAddress;
+    int unsigned RASDepth;
+    int unsigned BTBEntries;
+    int unsigned BHTEntries;
+    int unsigned InstrTlbEntries;
+    int unsigned DataTlbEntries;
+
     logic [63:0]                 DmBaseAddress;
     bit                          TvalEn;
     int unsigned                 NrPMPEntries;
@@ -258,6 +279,7 @@ package config_pkg;
     int unsigned ICACHE_LINE_WIDTH;
     int unsigned ICACHE_USER_LINE_WIDTH;
     cache_type_t DCacheType;
+    int unsigned DcacheIdWidth;
     int unsigned DCACHE_SET_ASSOC;
     int unsigned DCACHE_SET_ASSOC_WIDTH;
     int unsigned DCACHE_INDEX_WIDTH;

core/include/cv32a60x_config_pkg.sv

@@ -102,6 +102,8 @@ package cva6_config_pkg;
       CvxifEn: bit'(CVA6ConfigCvxifEn),
       RVZiCond: bit'(CVA6ConfigRVZiCond),
       NrScoreboardEntries: unsigned'(CVA6ConfigNrScoreboardEntries),
+      PerfCounterEn: bit'(CVA6ConfigPerfCounterEn),
+      MmuPresent: bit'(CVA6ConfigMmuPresent),
       RVS: bit'(1),
       RVU: bit'(1),
       HaltAddress: 64'h800,
@@ -137,7 +139,12 @@ package cva6_config_pkg;
       DcacheLineWidth: unsigned'(CVA6ConfigDcacheLineWidth),
       DataUserEn: unsigned'(CVA6ConfigDataUserEn),
       FetchUserWidth: unsigned'(CVA6ConfigFetchUserWidth),
-      FetchUserEn: unsigned'(CVA6ConfigFetchUserEn)
+      FetchUserEn: unsigned'(CVA6ConfigFetchUserEn),
+      InstrTlbEntries: int'(CVA6ConfigInstrTlbEntries),
+      DataTlbEntries: int'(CVA6ConfigDataTlbEntries),
+      NrLoadPipeRegs: int'(CVA6ConfigNrLoadPipeRegs),
+      NrStorePipeRegs: int'(CVA6ConfigNrStorePipeRegs),
+      DcacheIdWidth: int'(CVA6ConfigDcacheIdWidth)
   };
 
 endpackage