Bump core-v-verif d94f0de and fix questa simulator (#1915)

.github/workflows/ci.yml

@@ -13,7 +13,7 @@ jobs:
     env:
       NUM_JOBS: 8
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v4
       with:
         submodules: recursive
 
@@ -61,7 +61,7 @@ jobs:
     needs:
       build-riscv-tests
     steps:
-    - uses: actions/checkout@v2
+    - uses: actions/checkout@v4
       with:
         submodules: recursive
 
@@ -101,9 +101,8 @@ jobs:
           DV_SIMULATORS=${{matrix.target}} bash verif/regress/${{matrix.testcase}}.sh
 
     - name: Upload Lint Report to Github
-      uses: actions/upload-artifact@v3
+      uses: actions/upload-artifact@v4
       with:
         name: ${{matrix.target}}.${{matrix.testcase}}
         path: 'verif/sim/out*'
         retention-days: 10
-        compression-level: 9

.gitlab-ci.yml

@@ -119,7 +119,7 @@ build_tools:
     - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC
 
 .simu_after_script: &simu_after_script
-  - for i in $(find verif/sim/*/v*_sim -type f \( -name "*.csv" -o -name "*.iss" \)) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done
+  - for i in $(find verif/sim/out*/[vq]*_sim -type f \( -name "*.csv" -o -name "*.iss" \)) ; do head -10000 $i > artifacts/logs/$(basename $i).head ; done
   - head -10000 verif/sim/logfile.log > artifacts/logs/logfile.log.head
   - python3 .gitlab-ci/scripts/report_simu.py verif/sim/logfile.log
 

Makefile

@@ -84,6 +84,7 @@ endif
 ifneq ($(spike-tandem),)
     compile_flag += -define SPIKE_TANDEM
     CFLAGS += -I. -I$(SPIKE_INSTALL_DIR)/include/riscv
+    CFLAGS += -I. -I$(SPIKE_INSTALL_DIR)/include/disasm
     defines += +SPIKE_TANDEM=1
 endif
 
@@ -148,6 +149,8 @@ src :=  core/include/$(target)_config_pkg.sv
         $(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv)                   \
         $(if $(spike-tandem),verif/tb/core/uvma_cva6pkg_utils_pkg.sv)                \
         $(if $(spike-tandem),verif/tb/core/uvma_rvfi_pkg.sv)                         \
+        $(if $(spike-tandem),verif/tb/core/uvmc_rvfi_reference_model_pkg.sv)         \
+        $(if $(spike-tandem),verif/tb/core/uvmc_rvfi_scoreboard_pkg.sv)              \
         $(if $(spike-tandem),corev_apu/tb/common/spike.sv)                           \
         corev_apu/src/ariane.sv                                                      \
         $(wildcard corev_apu/bootrom/*.sv)                                           \
@@ -215,7 +218,7 @@ fpga_src :=  $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/b
 fpga_src := $(addprefix $(root-dir), $(fpga_src))
 
 # look for testbenches
-tbs := core/include/$(target)_config_pkg.sv corev_apu/tb/ariane_tb.sv corev_apu/tb/ariane_testharness.sv core/cva6_rvfi.sv
+tbs := corev_apu/tb/ariane_tb.sv corev_apu/tb/ariane_testharness.sv core/cva6_rvfi.sv
 
 tbs := $(addprefix $(root-dir), $(tbs))
 
@@ -239,15 +242,19 @@ incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REP
           $(CVA6_REPO_DIR)/corev_apu/register_interface/include/ $(CVA6_REPO_DIR)/corev_apu/tb/common/ \
           $(CVA6_REPO_DIR)/vendor/pulp-platform/axi/include/ \
           $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_rvfi/ \
+          $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_reference_model/ \
+          $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_scoreboard/ \
           $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl/ \
           $(CVA6_REPO_DIR)/verif/tb/core/ \
-          $(CVA6_REPO_DIR)/core/include/
+          $(CVA6_REPO_DIR)/core/include/ \
+          $(SPIKE_INSTALL_DIR)/include/disasm/
 
 # Compile and sim flags
-compile_flag     += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive -svinputport=compat +define+$(defines)
+compile_flag     += -incr -64 -nologo -quiet -suppress 13262 -suppress 8607 -permissive -svinputport=compat +define+$(defines) -suppress 8386
+vopt_flag +=  -incr -64 -nologo -quiet -suppress 13262 -permissive -svinputport=compat -t 1ns
 
-uvm-flags        += +UVM_NO_RELNOTES +UVM_VERBOSITY=LOW
-questa-flags     += -t 1ns -64 -coverage -classdebug $(gui-sim) $(QUESTASIM_FLAGS) +tohost_addr=$(tohost_addr)
+uvm-flags        += +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
+questa-flags     += -t 1ns -64 $(gui-sim) $(QUESTASIM_FLAGS) +tohost_addr=$(tohost_addr) +define+QUESTA
 compile_flag_vhd += -64 -nologo -quiet -2008
 
 # Iterate over all include directories and write them with +incdir+ prefixed
@@ -263,10 +270,12 @@ riscv-torture-bin    := java -jar sbt-launch.jar
 # if defined, calls the questa targets in batch mode
 ifdef batch-mode
 	questa-flags += -c
+        questa-cmd   += -do "run -all;"
+endif
+ifdef cov-mode
+        compile_flags += +cover=bcfst+/dut
+        questa-flags += -coverage
 	questa-cmd   := -do "coverage save -onexit tmp/$@.ucdb; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
-	questa-cmd   += -do " log -r /*; run -all;"
-else
-	questa-cmd   := -do " log -r /*; run -all;"
 endif
 # we want to preload the memories
 ifdef preload
@@ -305,7 +314,7 @@ vcs: vcs_build
 # Build the TB and module using QuestaSim
 build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
 	# Optimize top level
-	$(VOPT) $(compile_flag) -work $(library)  $(top_level) -o $(top_level)_optimized +acc -check_synthesis
+	$(VOPT) -64 -work $(library)  $(top_level) -o $(top_level)_optimized +acc -check_synthesis -dpilib $(SPIKE_INSTALL_DIR)/lib/libriscv -dpilib $(SPIKE_INSTALL_DIR)/lib/lifesvr -suppress 2085 -suppress 7063
 
 # src files
 $(library)/.build-srcs: $(library)
@@ -345,8 +354,9 @@ generate-trace-vsim:
 
 sim: build
 	$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
-	+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(SPIKE_INSTALL_DIR)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi  \
-	${top_level}_optimized +permissive-off ++$(elf_file) ++$(target-options) | tee sim.log
+	+BASEDIR=$(riscv-test-dir) $(uvm-flags) -sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv -sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \
+	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm  \
+	${top_level}_optimized +permissive-off +elf_file=$(elf_file) ++$(elf_file) ++$(target-options)
 
 $(riscv-asm-tests): build
 	$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
@@ -573,7 +583,7 @@ verilate_command := $(verilator) --no-timing verilator_config.vlt
                     $(if $(DEBUG), --trace-structs,)                                                             \
                     $(if $(TRACE_COMPACT), --trace-fst $(VL_INC_DIR)/verilated_fst_c.cpp)                        \
                     $(if $(TRACE_FAST), --trace $(VL_INC_DIR)/verilated_vcd_c.cpp)                               \
-                    -LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_INSTALL_DIR)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_INSTALL_DIR)/lib -lfesvr -lriscv $(if $(PROFILE), -g -pg,) -lpthread $(if $(TRACE_COMPACT), -lz,)" \
+                    -LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_INSTALL_DIR)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_INSTALL_DIR)/lib -lfesvr -lriscv -ldisasm $(if $(PROFILE), -g -pg,) -lpthread $(if $(TRACE_COMPACT), -lz,)" \
                     -CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) -DVL_DEBUG -I$(SPIKE_INSTALL_DIR)"               \
                     $(if $(SPIKE_TANDEM), +define+SPIKE_TANDEM, )                                                \
                     --cc --vpi                                                                                   \

ci/setup.sh

@@ -20,6 +20,13 @@ if [ -d ${VERILATOR_BUILD_DIR} ]; then
     make -C ${VERILATOR_BUILD_DIR} clean
 fi
 
+if [ -f ${SPIKE_PATH}/spike ]; then
+    spike_version="$(git -C ${SPIKE_SRC_DIR} log -1 --pretty=tformat:%h -- ${SPIKE_SRC_DIR}/..)"
+    spike_installed_version="$(${SPIKE_PATH}/spike -v |& cut -d ' ' -f 2)"
+    if [ "$spike_installed_version" != "$spike_version" ]; then
+        rm -rf ${SPIKE_INSTALL_DIR}
+    fi
+fi
 source verif/regress/install-spike.sh
 if [ -d ${SPIKE_SRC_DIR}/build/ ]; then
     make -C ${SPIKE_SRC_DIR}/build clean

core/commit_stage.sv

@@ -320,9 +320,12 @@ module commit_stage
         end
       end
     end
-    if (CVA6Cfg.RVZCMP)
-      commit_macro_ack_o = (commit_instr_i[0].is_macro_instr || commit_instr_i[1].is_macro_instr) ? commit_macro_ack : commit_ack_o;
-    else commit_macro_ack_o = commit_ack_o;
+    if (CVA6Cfg.RVZCMP) begin
+      if (CVA6Cfg.NrCommitPorts > 1)
+        commit_macro_ack_o = (commit_instr_i[0].is_macro_instr || commit_instr_i[1].is_macro_instr) ? commit_macro_ack : commit_ack_o;
+      else
+        commit_macro_ack_o = (commit_instr_i[0].is_macro_instr) ? commit_macro_ack : commit_ack_o;
+    end else commit_macro_ack_o = commit_ack_o;
   end
 
   // -----------------------------

core/cva6_rvfi_probes.sv

@@ -127,7 +127,3 @@ module cva6_rvfi_probes
 
 endmodule
 
-
-
-
-

core/include/config_pkg.sv

@@ -100,7 +100,7 @@ package config_pkg;
     int unsigned                 NrScoreboardEntries;
     // Address to jump when halt request
     logic [63:0]                 HaltAddress;
-    // Address to jump when exception 
+    // Address to jump when exception
     logic [63:0]                 ExceptionAddress;
     // Return address stack depth
     int unsigned                 RASDepth;
@@ -296,8 +296,8 @@ package config_pkg;
     // pragma translate_off
 `ifndef VERILATOR
     assert (Cfg.RASDepth > 0);
-    assert (2 ** $clog2(Cfg.BTBEntries) == Cfg.BTBEntries);
-    assert (2 ** $clog2(Cfg.BHTEntries) == Cfg.BHTEntries);
+    assert (Cfg.BTBEntries == 0 || (2 ** $clog2(Cfg.BTBEntries) == Cfg.BTBEntries));
+    assert (Cfg.BHTEntries == 0 || (2 ** $clog2(Cfg.BHTEntries) == Cfg.BHTEntries));
     assert (Cfg.NrNonIdempotentRules <= NrMaxRules);
     assert (Cfg.NrExecuteRegionRules <= NrMaxRules);
     assert (Cfg.NrCachedRegionRules <= NrMaxRules);

corev_apu/tb/ariane_tb.cpp

@@ -64,7 +64,6 @@ void handle_sigterm(int sig) {
 
 
 extern "C" void read_elf(const char* filename);
-extern "C" int64_t read_symbol(const char* symbol, uint64_t* address);
 extern "C" char get_section (long long* address, long long* len);
 extern "C" void read_section_void(long long address, void * buffer, uint64_t size = 0);
 

corev_apu/tb/ariane_tb.sv

@@ -23,9 +23,12 @@ import uvm_pkg::*;
 `define MAIN_MEM(P) dut.i_sram.gen_cut[0].i_tc_sram_wrapper.i_tc_sram.init_val[(``P``)]
 // `define USER_MEM(P) dut.i_sram.gen_cut[0].gen_mem.gen_mem_user.i_tc_sram_wrapper_user.i_tc_sram.init_val[(``P``)]
 
-import "DPI-C" function read_elf(input string filename);
+`ifndef READ_ELF_T
+`define READ_ELF_T
+import "DPI-C" function void read_elf(input string filename);
 import "DPI-C" function byte get_section(output longint address, output longint len);
 import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]);
+`endif
 
 module ariane_tb;
 

corev_apu/tb/ariane_testharness.sv

@@ -16,6 +16,12 @@
 `include "axi/assign.svh"
 `include "rvfi_types.svh"
 
+`ifdef VERILATOR
+`include "custom_uvm_macros.svh"
+`else
+`include "uvm_macros.svh"
+`endif
+
 module ariane_testharness #(
   parameter config_pkg::cva6_cfg_t CVA6Cfg = build_config_pkg::build_config(cva6_config_pkg::cva6_cfg),
   //
@@ -617,7 +623,7 @@ module ariane_testharness #(
   rvfi_probes_t rvfi_probes;
   rvfi_csr_t rvfi_csr;
   rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0]  rvfi_instr;
-  
+
   ariane #(
     .CVA6Cfg              ( CVA6Cfg             ),
     .rvfi_probes_instr_t  ( rvfi_probes_instr_t ),
@@ -664,8 +670,8 @@ module ariane_testharness #(
     end
   end
 
-  
- 
+
+
   cva6_rvfi #(
       .CVA6Cfg   (CVA6Cfg),
       .rvfi_instr_t(rvfi_instr_t),
@@ -700,18 +706,29 @@ module ariane_testharness #(
 `ifdef SPIKE_TANDEM
     spike #(
         .CVA6Cfg ( CVA6Cfg ),
-        .rvfi_instr_t(rvfi_instr_t)
+        .rvfi_instr_t(rvfi_instr_t),
+        .rvfi_csr_t(rvfi_csr_t)
     ) i_spike (
         .clk_i,
         .rst_ni,
         .clint_tick_i   ( rtc_i    ),
-        .rvfi_i         ( rvfi_instr )
+        .rvfi_i         ( rvfi_instr ),
+        .rvfi_csr_i     ( rvfi_csr )
     );
     initial begin
         $display("Running binary in tandem mode");
     end
 `endif
 
+`ifdef VERILATOR
+    initial begin
+        int verbosity = 0;
+        if ($value$plusargs("UVM_VERBOSITY=%s",verbosity)) begin
+            uvm_set_verbosity_level(verbosity);
+        end
+    end
+`endif
+
 
 `ifdef AXI_SVA
   // AXI 4 Assertion IP integration - You will need to get your own copy of this IP if you want