[RVFI] Optimize CSRs (#1999)

openhwgroup · Apr 15, 2024 · 71ef488 · 71ef488
1 parent e1ee77e
commit 71ef488
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Showing 5 changed files with 50 additions and 59 deletions.
diff --git a/core/cva6_rvfi.sv b/core/cva6_rvfi.sv
@@ -276,16 +276,13 @@ module cva6_rvfi
 
 
   `define CONNECT_RVFI_FULL(CSR_ENABLE_COND, CSR_NAME, CSR_SOURCE_NAME) \
-      bit [CVA6Cfg.XLEN-1:0] ``CSR_NAME``_d; \
       always_ff @(posedge clk_i) begin \
-        ``CSR_NAME``_d <= {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}; \
+        rvfi_csr_o.``CSR_NAME``.rdata  = CSR_ENABLE_COND ? {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} : 0; \
       end \
       always_comb begin \
-        rvfi_csr_o.``CSR_NAME = CSR_ENABLE_COND ? \
-        '{ rdata: ``CSR_NAME``_d , \
-          wdata: { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} }, \
-          rmask: '1, wmask: '1} \
-          : '0; \
+        rvfi_csr_o.``CSR_NAME``.wdata = CSR_ENABLE_COND ? { {{CVA6Cfg.XLEN-$bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME} } : 0; \
+        rvfi_csr_o.``CSR_NAME``.rmask = CSR_ENABLE_COND ? 1 : 0; \
+        rvfi_csr_o.``CSR_NAME``.wmask = CSR_ENABLE_COND ? (rvfi_csr_o.``CSR_NAME``.rdata != {{CVA6Cfg.XLEN - $bits(CSR_SOURCE_NAME)}, CSR_SOURCE_NAME}) : 0; \
       end
 
   `define COMMA ,
@@ -380,29 +377,7 @@ module cva6_rvfi
   genvar i;
   generate
     for (i = 0; i < 16; i++) begin
-      always_ff @(posedge clk_i) begin
-        pmpaddr_q[i] = (csr.pmpcfg_q[i].addr_mode[1] == 1'b1) ?
-            {{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
-            : {{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}} , csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1] , 1'b0 };
-      end
-      always_comb begin
-        rvfi_csr_o.pmpaddr[i] = '{
-            rdata: {'0, pmpaddr_q[i]},
-            wdata:
-            csr.pmpcfg_q[i].addr_mode[1]
-            == 1'b1 ?
-            {{CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}, csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0]}
-            : {
-            {CVA6Cfg.XLEN - (CVA6Cfg.PLEN - 2) {1'b0}}
-            ,
-            csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:1]
-            ,
-            1'b0
-            },
-            rmask: '1,
-            wmask: '1
-        };
-      end
+      `CONNECT_RVFI_FULL(1'b1, pmpaddr[i], csr.pmpaddr_q[i][CVA6Cfg.PLEN-3:0])
     end
   endgenerate
   ;

diff --git a/corev_apu/tb/common/spike.sv b/corev_apu/tb/common/spike.sv
@@ -46,12 +46,17 @@ module spike #(
     st_core_cntrl_cfg st;
 
     initial begin
+        string core_name = "cva6";
         st = cva6pkg_to_core_cntrl_cfg(st);
         st.boot_addr_valid = 1'b1;
         st.boot_addr = 64'h0x10000;
 
+        if ($test$plusargs("core_name")) begin
+          $value$plusargs("core_name=%s", core_name);
+        end
+
         rvfi_initialize(st);
-        rvfi_initialize_spike("cva6", st);
+        rvfi_initialize_spike(core_name, st);
 
     end
 
@@ -101,24 +106,30 @@ module spike #(
                         s_core.csr_wdata[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wdata;\
                         s_core.csr_wmask[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wmask;
 
-                    `GET_RVFI_CSR (CSR_MSTATUS  , mstatus     ,  0)
-                    `GET_RVFI_CSR (CSR_MCAUSE   , mcause      ,  1)
-                    `GET_RVFI_CSR (CSR_MEPC     , mepc        ,  2)
-                    `GET_RVFI_CSR (CSR_MTVEC    , mtvec       ,  3)
-                    `GET_RVFI_CSR (CSR_MISA     , misa        ,  4)
-                    `GET_RVFI_CSR (CSR_MTVAL    , mtval       ,  5)
-                    `GET_RVFI_CSR (CSR_MIDELEG  , mideleg     ,  6)
-                    `GET_RVFI_CSR (CSR_MEDELEG  , medeleg     ,  7)
-                    `GET_RVFI_CSR (CSR_SATP     , satp        ,  8)
-                    `GET_RVFI_CSR (CSR_MIE      , mie         ,  9)
-                    `GET_RVFI_CSR (CSR_STVEC    , stvec       , 10)
-                    `GET_RVFI_CSR (CSR_SSCRATCH , sscratch    , 11)
-                    `GET_RVFI_CSR (CSR_SEPC     , sepc        , 12)
-                    `GET_RVFI_CSR (CSR_MSCRATCH , mscratch    , 13)
-                    `GET_RVFI_CSR (CSR_STVAL    , stval       , 14)
-                    `GET_RVFI_CSR (CSR_SCAUSE   , scause      , 15)
-                    `GET_RVFI_CSR (CSR_PMPADDR0 , pmpaddr[0]  , 16)
-                    `GET_RVFI_CSR (CSR_PMPCFG0  , pmpcfg0     , 17)
+                    `GET_RVFI_CSR (CSR_MSTATUS      , mstatus     ,  0)
+                    `GET_RVFI_CSR (CSR_MCAUSE       , mcause      ,  1)
+                    `GET_RVFI_CSR (CSR_MEPC         , mepc        ,  2)
+                    `GET_RVFI_CSR (CSR_MTVEC        , mtvec       ,  3)
+                    `GET_RVFI_CSR (CSR_MISA         , misa        ,  4)
+                    `GET_RVFI_CSR (CSR_MTVAL        , mtval       ,  5)
+                    `GET_RVFI_CSR (CSR_MIDELEG      , mideleg     ,  6)
+                    `GET_RVFI_CSR (CSR_MEDELEG      , medeleg     ,  7)
+                    `GET_RVFI_CSR (CSR_SATP         , satp        ,  8)
+                    `GET_RVFI_CSR (CSR_MIE          , mie         ,  9)
+                    `GET_RVFI_CSR (CSR_STVEC        , stvec       , 10)
+                    `GET_RVFI_CSR (CSR_SSCRATCH     , sscratch    , 11)
+                    `GET_RVFI_CSR (CSR_SEPC         , sepc        , 12)
+                    `GET_RVFI_CSR (CSR_MSCRATCH     , mscratch    , 13)
+                    `GET_RVFI_CSR (CSR_STVAL        , stval       , 14)
+                    `GET_RVFI_CSR (CSR_SCAUSE       , scause      , 15)
+                    `GET_RVFI_CSR (CSR_PMPCFG0      , pmpcfg0     , 16)
+                    `GET_RVFI_CSR (CSR_PMPCFG1      , pmpcfg1     , 17)
+                    `GET_RVFI_CSR (CSR_PMPCFG2      , pmpcfg2     , 18)
+                    `GET_RVFI_CSR (CSR_PMPCFG3      , pmpcfg3     , 19)
+                    for (int i = 0; i < 16; i++) begin
+                      `GET_RVFI_CSR (CSR_PMPADDR0 + i  , pmpaddr[i]  , 20 + i)
+                    end
+                    `GET_RVFI_CSR (CSR_MINSTRET     , instret     , 37)
 
                     rvfi_spike_step(s_core, s_reference_model);
                     rvfi_compare(s_core, s_reference_model);

diff --git a/verif/regress/coremark.sh b/verif/regress/coremark.sh
@@ -31,11 +31,9 @@ if ! [ -n "$DV_SIMULATORS" ]; then
 fi
 
 if ! [ -n "$UVM_VERBOSITY" ]; then
-    UVM_VERBOSITY=UVM_NONE
+    export UVM_VERBOSITY=UVM_NONE
 fi
 
-export DV_OPTS="$DV_OPTS --issrun_opts=\"+UVM_VERBOSITY=$UVM_VERBOSITY\""
-
 make clean
 make -C verif/sim clean_all
 

diff --git a/verif/regress/smoke-tests.sh b/verif/regress/smoke-tests.sh
@@ -33,10 +33,10 @@ if ! [ -n "$DV_SIMULATORS" ]; then
 fi
 
 if ! [ -n "$UVM_VERBOSITY" ]; then
-    UVM_VERBOSITY=UVM_NONE
+    export UVM_VERBOSITY=UVM_NONE
 fi
 
-export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1+UVM_VERBOSITY=$UVM_VERBOSITY"
+export DV_OPTS="$DV_OPTS --issrun_opts=+debug_disable=1"
 
 cd verif/sim/
 python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS

diff --git a/verif/sim/Makefile b/verif/sim/Makefile
@@ -144,7 +144,7 @@ vcs-testharness:
 veri-testharness:
 	make -C $(path_var) verilate verilator="verilator --no-timing" target=$(target) defines=$(subst +define+,,$(isscomp_opts))
 	$(path_var)/work-ver/Variane_testharness $(if $(TRACE_COMPACT), -f verilator.fst) $(if $(TRACE_FAST), -v verilator.vcd) $(elf) $(issrun_opts) \
-	  +elf_file=$(elf) +tohost_addr=$(shell $$RISCV/bin/${CV_SW_PREFIX}nm -B $(elf) | grep -w tohost | cut -d' ' -f1)
+	  $(COMMON_PLUS_ARGS)
 	# If present, move default waveform files to log directory.
 	# Keep track of target in waveform file name.
 	[ ! -f verilator.fst ] || mv verilator.fst `dirname $(log)`/`basename $(log) .log`.fst
@@ -206,15 +206,22 @@ COMMON_COMP_UVM_FLAGS = \
 	  +incdir+$(CVA6_REPO_DIR)/verif/env/uvme +incdir+$(CVA6_REPO_DIR)/verif/tb/uvmt \
 	  $(if $(spike-tandem), +define+SPIKE_TANDEM=1)
 
-COMMON_RUN_UVM_FLAGS = \
-	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv \
-	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \
-	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm \
+COMMON_PLUS_ARGS = \
 	++$(elf) \
 	+elf_file=$(elf) \
 	+tohost_addr=$(shell $$RISCV/bin/$(CV_SW_PREFIX)nm -B $(elf) | grep -w tohost | cut -d' ' -f1) \
 	+signature=$(elf).signature_output  +UVM_TESTNAME=uvmt_cva6_firmware_test_c
 
+ifneq ($(UVM_VERBOSITY),)
+COMMON_PLUS_ARGS += +UVM_VERBOSITY=$(UVM_VERBOSITY)
+endif
+
+COMMON_RUN_UVM_FLAGS = \
+	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv \
+	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \
+	-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm \
+	$(COMMON_PLUS_ARGS)
+
 ALL_UVM_FLAGS   = -lca -sverilog +incdir+$(VCS_HOME)/etc/uvm/src \
 	  $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv -ntb_opts uvm-1.2 -timescale=1ns/1ps \
 	  -assert svaext -race=all -ignore unique_checks -full64 -q +incdir+$(VCS_HOME)/etc/uvm/src \