Parametrization step 3 (#1935)

This is the third step for #1451. Many values are moved but not all values are moved yet

* move NR_SB_ENTRIES & TRANS_ID_BITS
* remove default rvfi_instr_t from spike.sv
* fifo_v3: ariane_pkg::FPGA_EN becomes a param
* move FPGA_EN
* inline wt_cache_pkg::L15_SET_ASSOC
* move wt_cache_pkg::L15_WAY_WIDTH
* inline wt_cache_pkg::L1I_SET_ASSOC
* inline wt_cache_pkg::L1D_SET_ASSOC
* move wt_cache_pkg::DCACHE_CL_IDX_WIDTH
* move ICACHE_TAG_WIDTH
* move DCACHE_TAG_WIDTH
* move ICACHE_INDEX_WIDTH
* move ICACHE_SET_ASSOC
* use ICACHE_SET_ASSOC_WIDTH instead of $clog2(ICACHE_SET_ASSOC)
* move DCACHE_NUM_WORDS
* move DCACHE_INDEX_WIDTH
* move DCACHE_OFFSET_WIDTH
* move DCACHE_BYTE_OFFSET
* move DCACHE_DIRTY_WIDTH
* move DCACHE_SET_ASSOC_WIDTH
* move DCACHE_SET_ASSOC
* move CONFIG_L1I_SIZE
* move CONFIG_L1D_SIZE
* move DCACHE_LINE_WIDTH
* move ICACHE_LINE_WIDTH
* move ICACHE_USER_LINE_WIDTH
* move DCACHE_USER_LINE_WIDTH
* DATA_USER_WIDTH = DCACHE_USER_WIDTH
* move DCACHE_USER_WIDTH
* move FETCH_USER_WIDTH
* move FETCH_USER_EN
* move LOG2_INSTR_PER_FETCH
* move INSTR_PER_FETCH
* move FETCH_WIDTH
* transform SSTATUS_SD and SMODE_STATUS_READ_MASK into functions
* move [SM]_{SW,TIMER,EXT}_INTERRUPT into a structure
* move SV
* move vm_mode_t to config_pkg
* move MODE_SV
* move VPN2
* move PPNW
* move ASIDW
* move ModeW
* move XLEN_ALIGN_BYTES
* move DATA_USER_EN
* format: apply verible

common/local/util/ex_trace_item.svh

@@ -14,7 +14,9 @@
 
 `ifndef VERILATOR
 class ex_trace_item #(
-    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty
+    parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
+    parameter type interrupts_t = logic,
+    parameter interrupts_t INTERRUPTS = '0
 );
 
     // contains a human readable form of the cause value
@@ -42,12 +44,12 @@ class ex_trace_item #(
             riscv::INSTR_PAGE_FAULT:      this.cause_s = "Instruction Page Fault";
             riscv::LOAD_PAGE_FAULT:       this.cause_s = "Load Page Fault";
             riscv::STORE_PAGE_FAULT:      this.cause_s = "Store Page Fault";
-            riscv::S_SW_INTERRUPT:        this.cause_s = "Supervisor Software Interrupt";
-            riscv::M_SW_INTERRUPT:        this.cause_s = "Machine Software Interrupt";
-            riscv::S_TIMER_INTERRUPT:     this.cause_s = "Supervisor Timer Interrupt";
-            riscv::M_TIMER_INTERRUPT:     this.cause_s = "Machine Timer Interrupt";
-            riscv::S_EXT_INTERRUPT:       this.cause_s = "Supervisor External Interrupt";
-            riscv::M_EXT_INTERRUPT:       this.cause_s = "Machine External Interrupt";
+            INTERRUPTS.S_SW:              this.cause_s = "Supervisor Software Interrupt";
+            INTERRUPTS.M_SW:              this.cause_s = "Machine Software Interrupt";
+            INTERRUPTS.S_TIMER:           this.cause_s = "Supervisor Timer Interrupt";
+            INTERRUPTS.M_TIMER:           this.cause_s = "Machine Timer Interrupt";
+            INTERRUPTS.S_EXT:             this.cause_s = "Supervisor External Interrupt";
+            INTERRUPTS.M_EXT:             this.cause_s = "Machine External Interrupt";
             riscv::DEBUG_REQUEST:         this.cause_s = "Request Debug Mode";
             default: this.cause_s = "Interrupt";
         endcase
@@ -64,12 +66,12 @@ class ex_trace_item #(
                 riscv::ENV_CALL_MMODE,
                 riscv::ENV_CALL_SMODE,
                 riscv::ENV_CALL_UMODE,
-                riscv::S_SW_INTERRUPT,
-                riscv::M_SW_INTERRUPT,
-                riscv::S_TIMER_INTERRUPT,
-                riscv::M_TIMER_INTERRUPT,
-                riscv::S_EXT_INTERRUPT,
-                riscv::M_EXT_INTERRUPT
+                INTERRUPTS.S_SW,
+                INTERRUPTS.M_SW,
+                INTERRUPTS.S_TIMER,
+                INTERRUPTS.M_TIMER,
+                INTERRUPTS.S_EXT,
+                INTERRUPTS.M_EXT
             }))
             s = $sformatf("%s, \n\t\t\t\ttval: %h", s, this.tval);
         return s;

common/local/util/instr_tracer.sv

@@ -20,7 +20,9 @@
 module instr_tracer #(
   parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
   parameter type bp_resolve_t = logic,
-  parameter type scoreboard_entry_t = logic
+  parameter type scoreboard_entry_t = logic,
+  parameter type interrupts_t = logic,
+  parameter interrupts_t INTERRUPTS = '0
 )(
   instr_tracer_if tracer_if,
   input logic[riscv::XLEN-1:0] hart_id_i
@@ -206,7 +208,9 @@ module instr_tracer #(
 
   function void printException(logic [riscv::VLEN-1:0] pc, logic [63:0] cause, logic [63:0] tval);
     automatic ex_trace_item #(
-      .CVA6Cfg(CVA6Cfg)
+      .CVA6Cfg(CVA6Cfg),
+      .interrupts_t(interrupts_t),
+      .INTERRUPTS(INTERRUPTS)
     ) eti = new (pc, cause, tval);
     automatic string print_ex = eti.printException();
     $fwrite(f, {print_ex, "\n"});

core/acc_dispatcher.sv

@@ -24,34 +24,34 @@ module acc_dispatcher
     parameter type fu_data_t = logic,
     parameter type scoreboard_entry_t = logic,
     localparam type accelerator_req_t = struct packed {
-      logic                                 req_valid;
-      logic                                 resp_ready;
-      riscv::instruction_t                  insn;
-      logic [riscv::XLEN-1:0]               rs1;
-      logic [riscv::XLEN-1:0]               rs2;
-      fpnew_pkg::roundmode_e                frm;
-      logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
-      logic                                 store_pending;
+      logic                             req_valid;
+      logic                             resp_ready;
+      riscv::instruction_t              insn;
+      logic [riscv::XLEN-1:0]           rs1;
+      logic [riscv::XLEN-1:0]           rs2;
+      fpnew_pkg::roundmode_e            frm;
+      logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
+      logic                             store_pending;
       // Invalidation interface
-      logic                                 acc_cons_en;
-      logic                                 inval_ready;
+      logic                             acc_cons_en;
+      logic                             inval_ready;
     },
     parameter type acc_req_t = accelerator_req_t,
     parameter type acc_resp_t = struct packed {
-      logic                                 req_ready;
-      logic                                 resp_valid;
-      logic [riscv::XLEN-1:0]               result;
-      logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
-      logic                                 error;
+      logic                             req_ready;
+      logic                             resp_valid;
+      logic [riscv::XLEN-1:0]           result;
+      logic [CVA6Cfg.TRANS_ID_BITS-1:0] trans_id;
+      logic                             error;
       // Metadata
-      logic                                 store_pending;
-      logic                                 store_complete;
-      logic                                 load_complete;
-      logic [4:0]                           fflags;
-      logic                                 fflags_valid;
+      logic                             store_pending;
+      logic                             store_complete;
+      logic                             load_complete;
+      logic [4:0]                       fflags;
+      logic                             fflags_valid;
       // Invalidation interface
-      logic                                 inval_valid;
-      logic [63:0]                          inval_addr;
+      logic                             inval_valid;
+      logic [63:0]                      inval_addr;
     },
     parameter type acc_cfg_t = logic,
     parameter acc_cfg_t AccCfg = '0
@@ -75,7 +75,7 @@ module acc_dispatcher
     output logic issue_stall_o,
     input fu_data_t fu_data_i,
     input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
-    output logic [TRANS_ID_BITS-1:0] acc_trans_id_o,
+    output logic [CVA6Cfg.TRANS_ID_BITS-1:0] acc_trans_id_o,
     output logic [riscv::XLEN-1:0] acc_result_o,
     output logic acc_valid_o,
     output exception_t acc_exception_o,
@@ -161,14 +161,15 @@ module acc_dispatcher
   logic                                            acc_insn_queue_empty;
   logic     [idx_width(InstructionQueueDepth)-1:0] acc_insn_queue_usage;
   logic                                            acc_commit;
-  logic     [                   TRANS_ID_BITS-1:0] acc_commit_trans_id;
+  logic     [           CVA6Cfg.TRANS_ID_BITS-1:0] acc_commit_trans_id;
 
   assign acc_data = acc_valid_ex_o ? fu_data_i : '0;
 
   fifo_v3 #(
       .DEPTH       (InstructionQueueDepth),
       .FALL_THROUGH(1'b1),
-      .dtype       (fu_data_t)
+      .dtype       (fu_data_t),
+      .FPGA_EN     (CVA6Cfg.FPGA_EN)
   ) i_acc_insn_queue (
       .clk_i     (clk_i),
       .rst_ni    (rst_ni),
@@ -191,13 +192,13 @@ module acc_dispatcher
    **********************************/
 
   // Keep track of the instructions that were received by the dispatcher.
-  logic [NR_SB_ENTRIES-1:0] insn_pending_d, insn_pending_q;
+  logic [CVA6Cfg.NR_SB_ENTRIES-1:0] insn_pending_d, insn_pending_q;
   `FF(insn_pending_q, insn_pending_d, '0)
 
   // Only non-speculative instructions can be issued to the accelerators.
   // The following block keeps track of which transaction IDs reached the
   // top of the scoreboard, and are therefore no longer speculative.
-  logic [NR_SB_ENTRIES-1:0] insn_ready_d, insn_ready_q;
+  logic [CVA6Cfg.NR_SB_ENTRIES-1:0] insn_ready_d, insn_ready_q;
   `FF(insn_ready_q, insn_ready_d, '0)
 
   always_comb begin : p_non_speculative_ff

core/amo_buffer.sv

@@ -63,8 +63,9 @@ module amo_buffer #(
   assign flush_amo_buffer = flush_i & !amo_valid_commit_i;
 
   fifo_v3 #(
-      .DEPTH(1),
-      .dtype(amo_op_t)
+      .DEPTH  (1),
+      .dtype  (amo_op_t),
+      .FPGA_EN(CVA6Cfg.FPGA_EN)
   ) i_amo_fifo (
       .clk_i     (clk_i),
       .rst_ni    (rst_ni),

core/cache_subsystem/cache_ctrl.sv

@@ -37,15 +37,15 @@ module cache_ctrl
     input dcache_req_i_t req_port_i,
     output dcache_req_o_t req_port_o,
     // SRAM interface
-    output logic [DCACHE_SET_ASSOC-1:0] req_o,  // req is valid
-    output logic [DCACHE_INDEX_WIDTH-1:0] addr_o,  // address into cache array
+    output logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] req_o,  // req is valid
+    output logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] addr_o,  // address into cache array
     input logic gnt_i,
     output cache_line_t data_o,
     output cl_be_t be_o,
-    output logic [DCACHE_TAG_WIDTH-1:0] tag_o,  //valid one cycle later
-    input cache_line_t [DCACHE_SET_ASSOC-1:0] data_i,
+    output logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0] tag_o,  //valid one cycle later
+    input cache_line_t [CVA6Cfg.DCACHE_SET_ASSOC-1:0] data_i,
     output logic we_o,
-    input logic [DCACHE_SET_ASSOC-1:0] hit_way_i,
+    input logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] hit_way_i,
     // Miss handling
     output miss_req_t miss_req_o,
     // return
@@ -79,29 +79,30 @@ module cache_ctrl
       state_d, state_q;
 
   typedef struct packed {
-    logic [DCACHE_INDEX_WIDTH-1:0] index;
-    logic [DCACHE_TAG_WIDTH-1:0]   tag;
-    logic [DCACHE_TID_WIDTH-1:0]   id;
-    logic [7:0]                    be;
-    logic [1:0]                    size;
-    logic                          we;
-    logic [63:0]                   wdata;
-    logic                          bypass;
-    logic                          killed;
+    logic [CVA6Cfg.DCACHE_INDEX_WIDTH-1:0] index;
+    logic [CVA6Cfg.DCACHE_TAG_WIDTH-1:0]   tag;
+    logic [DCACHE_TID_WIDTH-1:0]           id;
+    logic [7:0]                            be;
+    logic [1:0]                            size;
+    logic                                  we;
+    logic [63:0]                           wdata;
+    logic                                  bypass;
+    logic                                  killed;
   } mem_req_t;
 
-  logic [DCACHE_SET_ASSOC-1:0] hit_way_d, hit_way_q;
+  logic [CVA6Cfg.DCACHE_SET_ASSOC-1:0] hit_way_d, hit_way_q;
 
   mem_req_t mem_req_d, mem_req_q;
 
   assign busy_o = (state_q != IDLE);
   assign tag_o  = mem_req_d.tag;
 
-  logic [DCACHE_LINE_WIDTH-1:0] cl_i;
+  logic [CVA6Cfg.DCACHE_LINE_WIDTH-1:0] cl_i;
 
   always_comb begin : way_select
     cl_i = '0;
-    for (int unsigned i = 0; i < DCACHE_SET_ASSOC; i++) if (hit_way_i[i]) cl_i = data_i[i].data;
+    for (int unsigned i = 0; i < CVA6Cfg.DCACHE_SET_ASSOC; i++)
+    if (hit_way_i[i]) cl_i = data_i[i].data;
 
     // cl_i = data_i[one_hot_to_bin(hit_way_i)].data;
   end
@@ -110,10 +111,10 @@ module cache_ctrl
   // Cache FSM
   // --------------
   always_comb begin : cache_ctrl_fsm
-    automatic logic [$clog2(DCACHE_LINE_WIDTH)-1:0] cl_offset;
+    automatic logic [$clog2(CVA6Cfg.DCACHE_LINE_WIDTH)-1:0] cl_offset;
     // incoming cache-line -> this is needed as synthesis is not supporting +: indexing in a multi-dimensional array
     // cache-line offset -> multiple of 64
-    cl_offset = mem_req_q.index[DCACHE_BYTE_OFFSET-1:3] << 6;  // shift by 6 to the left
+    cl_offset = mem_req_q.index[CVA6Cfg.DCACHE_OFFSET_WIDTH-1:3] << 6;  // shift by 6 to the left
     // default assignments
     state_d = state_q;
     mem_req_d = mem_req_q;
@@ -256,7 +257,7 @@ module cache_ctrl
           // Check for cache-ability
           // -------------------------
           if (!config_pkg::is_inside_cacheable_regions(
-                  CVA6Cfg, {{{64 - riscv::PLEN} {1'b0}}, tag_o, {DCACHE_INDEX_WIDTH{1'b0}}}
+                  CVA6Cfg, {{{64 - riscv::PLEN} {1'b0}}, tag_o, {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}}
               )) begin
             mem_req_d.bypass = 1'b1;
             state_d = WAIT_REFILL_GNT;
@@ -460,7 +461,7 @@ module cache_ctrl
   //pragma translate_off
 `ifndef VERILATOR
   initial begin
-    assert (DCACHE_LINE_WIDTH == 128)
+    assert (CVA6Cfg.DCACHE_LINE_WIDTH == 128)
     else
       $error(
           "Cacheline width has to be 128 for the moment. But only small changes required in data select logic"

core/cache_subsystem/cva6_hpdcache_if_adapter.sv

@@ -67,9 +67,9 @@ module cva6_hpdcache_if_adapter
       assign hpdcache_req_is_uncacheable = !config_pkg::is_inside_cacheable_regions(
           CVA6Cfg,
           {
-            {64 - ariane_pkg::DCACHE_TAG_WIDTH{1'b0}}
+            {64 - CVA6Cfg.DCACHE_TAG_WIDTH{1'b0}}
             , cva6_req_i.address_tag
-            , {ariane_pkg::DCACHE_INDEX_WIDTH{1'b0}}
+            , {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}
           }
       );
 
@@ -140,9 +140,9 @@ module cva6_hpdcache_if_adapter
       assign hpdcache_req_is_uncacheable = !config_pkg::is_inside_cacheable_regions(
           CVA6Cfg,
           {
-            {64 - ariane_pkg::DCACHE_TAG_WIDTH{1'b0}}
+            {64 - CVA6Cfg.DCACHE_TAG_WIDTH{1'b0}}
             , hpdcache_req_o.addr_tag,
-            {ariane_pkg::DCACHE_INDEX_WIDTH{1'b0}}
+            {CVA6Cfg.DCACHE_INDEX_WIDTH{1'b0}}
           }
       );
 

core/cache_subsystem/cva6_hpdcache_subsystem.sv

@@ -520,8 +520,7 @@ module cva6_hpdcache_subsystem
   //  AXI arbiter instantiation
   //  {{{
   cva6_hpdcache_subsystem_axi_arbiter #(
-      .HPDcacheMemIdWidth   (CVA6Cfg.MEM_TID_WIDTH),
-      .HPDcacheMemDataWidth (CVA6Cfg.AxiDataWidth),
+      .CVA6Cfg              (CVA6Cfg),
       .hpdcache_mem_req_t   (hpdcache_mem_req_t),
       .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t),
       .hpdcache_mem_resp_r_t(hpdcache_mem_resp_r_t),