move functions into modules (#1926)

core/acc_dispatcher.sv

@@ -27,8 +27,8 @@ module acc_dispatcher
       logic                                 req_valid;
       logic                                 resp_ready;
       riscv::instruction_t                  insn;
-      riscv::xlen_t                         rs1;
-      riscv::xlen_t                         rs2;
+      logic [riscv::XLEN-1:0]               rs1;
+      logic [riscv::XLEN-1:0]               rs2;
       fpnew_pkg::roundmode_e                frm;
       logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
       logic                                 store_pending;
@@ -40,7 +40,7 @@ module acc_dispatcher
     parameter type acc_resp_t = struct packed {
       logic                                 req_ready;
       logic                                 resp_valid;
-      riscv::xlen_t                         result;
+      logic [riscv::XLEN-1:0]               result;
       logic [ariane_pkg::TRANS_ID_BITS-1:0] trans_id;
       logic                                 error;
       // Metadata
@@ -76,7 +76,7 @@ module acc_dispatcher
     input fu_data_t fu_data_i,
     input scoreboard_entry_t [CVA6Cfg.NrCommitPorts-1:0] commit_instr_i,
     output logic [TRANS_ID_BITS-1:0] acc_trans_id_o,
-    output xlen_t acc_result_o,
+    output logic [riscv::XLEN-1:0] acc_result_o,
     output logic acc_valid_o,
     output exception_t acc_exception_o,
     // Interface with the execute stage

core/alu.sv

@@ -31,24 +31,24 @@ module alu
     // FU data needed to execute instruction - ISSUE_STAGE
     input fu_data_t fu_data_i,
     // ALU result - ISSUE_STAGE
-    output riscv::xlen_t result_o,
+    output logic [riscv::XLEN-1:0] result_o,
     // ALU branch compare result - branch_unit
     output logic alu_branch_res_o
 );
 
-  riscv::xlen_t                   operand_a_rev;
-  logic         [           31:0] operand_a_rev32;
-  logic         [  riscv::XLEN:0] operand_b_neg;
-  logic         [riscv::XLEN+1:0] adder_result_ext_o;
-  logic                           less;  // handles both signed and unsigned forms
-  logic         [           31:0] rolw;  // Rotate Left Word
-  logic         [           31:0] rorw;  // Rotate Right Word
+  logic [riscv::XLEN-1:0] operand_a_rev;
+  logic [           31:0] operand_a_rev32;
+  logic [  riscv::XLEN:0] operand_b_neg;
+  logic [riscv::XLEN+1:0] adder_result_ext_o;
+  logic                   less;  // handles both signed and unsigned forms
+  logic [           31:0] rolw;  // Rotate Left Word
+  logic [           31:0] rorw;  // Rotate Right Word
   logic [31:0] orcbw, rev8w;
   logic [  $clog2(riscv::XLEN) : 0] cpop;  // Count Population
   logic [$clog2(riscv::XLEN)-1 : 0] lz_tz_count;  // Count Leading Zeros
   logic [                      4:0] lz_tz_wcount;  // Count Leading Zeros Word
   logic lz_tz_empty, lz_tz_wempty;
-  riscv::xlen_t orcbw_result, rev8w_result;
+  logic [riscv::XLEN-1:0] orcbw_result, rev8w_result;
 
   // bit reverse operand_a for left shifts and bit counting
   generate
@@ -65,7 +65,7 @@ module alu
   logic adder_op_b_negate;
   logic adder_z_flag;
   logic [riscv::XLEN:0] adder_in_a, adder_in_b;
-  riscv::xlen_t adder_result;
+  logic [riscv::XLEN-1:0] adder_result;
   logic [riscv::XLEN-1:0] operand_a_bitmanip, bit_indx;
 
   always_comb begin
@@ -132,21 +132,21 @@ module alu
   // ---------
 
   // TODO: this can probably optimized significantly
-  logic                         shift_left;  // should we shift left
-  logic                         shift_arithmetic;
+  logic                   shift_left;  // should we shift left
+  logic                   shift_arithmetic;
 
-  riscv::xlen_t                 shift_amt;  // amount of shift, to the right
-  riscv::xlen_t                 shift_op_a;  // input of the shifter
-  logic         [         31:0] shift_op_a32;  // input to the 32 bit shift operation
+  logic [riscv::XLEN-1:0] shift_amt;  // amount of shift, to the right
+  logic [riscv::XLEN-1:0] shift_op_a;  // input of the shifter
+  logic [           31:0] shift_op_a32;  // input to the 32 bit shift operation
 
-  riscv::xlen_t                 shift_result;
-  logic         [         31:0] shift_result32;
+  logic [riscv::XLEN-1:0] shift_result;
+  logic [           31:0] shift_result32;
 
-  logic         [riscv::XLEN:0] shift_right_result;
-  logic         [         32:0] shift_right_result32;
+  logic [  riscv::XLEN:0] shift_right_result;
+  logic [           32:0] shift_right_result32;
 
-  riscv::xlen_t                 shift_left_result;
-  logic         [         31:0] shift_left_result32;
+  logic [riscv::XLEN-1:0] shift_left_result;
+  logic [           31:0] shift_left_result32;
 
   assign shift_amt = fu_data_i.operand_b;
 

core/amo_buffer.sv

@@ -25,7 +25,7 @@ module amo_buffer #(
     output logic ready_o,  // AMO unit is ready
     input ariane_pkg::amo_t amo_op_i,  // AMO Operation
     input  logic [riscv::PLEN-1:0]      paddr_i,            // physical address of store which needs to be placed in the queue
-    input riscv::xlen_t data_i,  // data which is placed in the queue
+    input logic [riscv::XLEN-1:0] data_i,  // data which is placed in the queue
     input logic [1:0] data_size_i,  // type of request we are making (e.g.: bytes to write)
     // D$
     output ariane_pkg::amo_req_t amo_req_o,  // request to cache subsytem
@@ -40,7 +40,7 @@ module amo_buffer #(
   typedef struct packed {
     ariane_pkg::amo_t       op;
     logic [riscv::PLEN-1:0] paddr;
-    riscv::xlen_t           data;
+    logic [riscv::XLEN-1:0] data;
     logic [1:0]             size;
   } amo_op_t;
 

core/cache_subsystem/cva6_hpdcache_subsystem.sv

@@ -137,7 +137,7 @@ module cva6_hpdcache_subsystem
   logic icache_miss_resp_valid;
   icache_rtrn_t icache_miss_resp;
 
-  localparam int ICACHE_RDTXID = 1 << (ariane_pkg::MEM_TID_WIDTH - 1);
+  localparam int ICACHE_RDTXID = 1 << (CVA6Cfg.MEM_TID_WIDTH - 1);
 
   cva6_icache #(
       .CVA6Cfg(CVA6Cfg),
@@ -182,7 +182,7 @@ module cva6_hpdcache_subsystem
   localparam int HPDCACHE_NREQUESTERS = NumPorts + 2;
 
   typedef logic [riscv::PLEN-1:0] hpdcache_mem_addr_t;
-  typedef logic [ariane_pkg::MEM_TID_WIDTH-1:0] hpdcache_mem_id_t;
+  typedef logic [CVA6Cfg.MEM_TID_WIDTH-1:0] hpdcache_mem_id_t;
   typedef logic [CVA6Cfg.AxiDataWidth-1:0] hpdcache_mem_data_t;
   typedef logic [CVA6Cfg.AxiDataWidth/8-1:0] hpdcache_mem_be_t;
   `HPDCACHE_TYPEDEF_MEM_REQ_T(hpdcache_mem_req_t, hpdcache_mem_addr_t, hpdcache_mem_id_t);
@@ -426,7 +426,7 @@ module cva6_hpdcache_subsystem
   hpdcache #(
       .NREQUESTERS         (HPDCACHE_NREQUESTERS),
       .HPDcacheMemAddrWidth(riscv::PLEN),
-      .HPDcacheMemIdWidth  (ariane_pkg::MEM_TID_WIDTH),
+      .HPDcacheMemIdWidth  (CVA6Cfg.MEM_TID_WIDTH),
       .HPDcacheMemDataWidth(CVA6Cfg.AxiDataWidth)
   ) i_hpdcache (
       .clk_i,
@@ -520,7 +520,7 @@ module cva6_hpdcache_subsystem
   //  AXI arbiter instantiation
   //  {{{
   cva6_hpdcache_subsystem_axi_arbiter #(
-      .HPDcacheMemIdWidth   (ariane_pkg::MEM_TID_WIDTH),
+      .HPDcacheMemIdWidth   (CVA6Cfg.MEM_TID_WIDTH),
       .HPDcacheMemDataWidth (CVA6Cfg.AxiDataWidth),
       .hpdcache_mem_req_t   (hpdcache_mem_req_t),
       .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t),

core/cache_subsystem/cva6_icache.sv

@@ -37,7 +37,7 @@ module cva6_icache
     parameter type icache_req_t = logic,
     parameter type icache_rtrn_t = logic,
     /// ID to be used for read transactions
-    parameter logic [MEM_TID_WIDTH-1:0] RdTxId = 0
+    parameter logic [CVA6Cfg.MEM_TID_WIDTH-1:0] RdTxId = 0
 ) (
     input logic clk_i,
     input logic rst_ni,
@@ -62,6 +62,10 @@ module cva6_icache
     output icache_req_t  mem_data_o
 );
 
+  localparam ICACHE_OFFSET_WIDTH = $clog2(ariane_pkg::ICACHE_LINE_WIDTH / 8);
+  localparam ICACHE_NUM_WORDS = 2 ** (ariane_pkg::ICACHE_INDEX_WIDTH - ICACHE_OFFSET_WIDTH);
+  localparam ICACHE_CL_IDX_WIDTH = $clog2(ICACHE_NUM_WORDS);  // excluding byte offset
+
   // functions
   function automatic logic [ariane_pkg::ICACHE_SET_ASSOC-1:0] icache_way_bin2oh(
       input logic [L1I_WAY_WIDTH-1:0] in);
@@ -551,8 +555,8 @@ module cva6_icache
   else $fatal(1, "[l1 icache] cl_hit signal must be hot1");
 
   // this is only used for verification!
-  logic vld_mirror[wt_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
-  logic [ariane_pkg::ICACHE_TAG_WIDTH-1:0] tag_mirror[wt_cache_pkg::ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
+  logic vld_mirror[ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
+  logic [ariane_pkg::ICACHE_TAG_WIDTH-1:0] tag_mirror[ICACHE_NUM_WORDS-1:0][ariane_pkg::ICACHE_SET_ASSOC-1:0];
   logic [ariane_pkg::ICACHE_SET_ASSOC-1:0] tag_write_duplicate_test;
 
   always_ff @(posedge clk_i or negedge rst_ni) begin : p_mirror

core/cache_subsystem/miss_handler.sv

@@ -71,6 +71,26 @@ module miss_handler
   // Three MSHR ports + AMO port
   parameter NR_BYPASS_PORTS = NR_PORTS + 1;
 
+  // convert one hot to bin for -> needed for cache replacement
+  function automatic logic [std_cache_pkg::DCACHE_SET_ASSOC_WIDTH-1:0] one_hot_to_bin(
+      input logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] in);
+    for (int unsigned i = 0; i < ariane_pkg::DCACHE_SET_ASSOC; i++) begin
+      if (in[i]) return i;
+    end
+  endfunction
+  // get the first bit set, returns one hot value
+  function automatic logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] get_victim_cl(
+      input logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] valid_dirty);
+    // one-hot return vector
+    logic [ariane_pkg::DCACHE_SET_ASSOC-1:0] oh = '0;
+    for (int unsigned i = 0; i < ariane_pkg::DCACHE_SET_ASSOC; i++) begin
+      if (valid_dirty[i]) begin
+        oh[i] = 1'b1;
+        return oh;
+      end
+    end
+  endfunction
+
   // FSM states
   enum logic [3:0] {
     IDLE,                // 0

core/cache_subsystem/wt_axi_adapter.sv

@@ -97,9 +97,9 @@ module wt_axi_adapter
   // AMO generates r beat
   logic amo_gen_r_d, amo_gen_r_q;
 
-  logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] icache_rtrn_tid_d, icache_rtrn_tid_q;
-  logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_tid_d, dcache_rtrn_tid_q;
-  logic [wt_cache_pkg::CACHE_ID_WIDTH-1:0] dcache_rtrn_rd_tid, dcache_rtrn_wr_tid;
+  logic [CVA6Cfg.MEM_TID_WIDTH-1:0] icache_rtrn_tid_d, icache_rtrn_tid_q;
+  logic [CVA6Cfg.MEM_TID_WIDTH-1:0] dcache_rtrn_tid_d, dcache_rtrn_tid_q;
+  logic [CVA6Cfg.MEM_TID_WIDTH-1:0] dcache_rtrn_rd_tid, dcache_rtrn_wr_tid;
   logic dcache_rd_pop, dcache_wr_pop;
   logic icache_rd_full, icache_rd_empty;
   logic dcache_rd_full, dcache_rd_empty;
@@ -352,7 +352,7 @@ module wt_axi_adapter
   logic icache_rtrn_vld_d, icache_rtrn_vld_q, dcache_rtrn_vld_d, dcache_rtrn_vld_q;
 
   fifo_v3 #(
-      .DATA_WIDTH(wt_cache_pkg::CACHE_ID_WIDTH),
+      .DATA_WIDTH(CVA6Cfg.MEM_TID_WIDTH),
       .DEPTH     (MetaFifoDepth)
   ) i_rd_icache_id (
       .clk_i     (clk_i),
@@ -369,7 +369,7 @@ module wt_axi_adapter
   );
 
   fifo_v3 #(
-      .DATA_WIDTH(wt_cache_pkg::CACHE_ID_WIDTH),
+      .DATA_WIDTH(CVA6Cfg.MEM_TID_WIDTH),
       .DEPTH     (MetaFifoDepth)
   ) i_rd_dcache_id (
       .clk_i     (clk_i),
@@ -386,7 +386,7 @@ module wt_axi_adapter
   );
 
   fifo_v3 #(
-      .DATA_WIDTH(wt_cache_pkg::CACHE_ID_WIDTH),
+      .DATA_WIDTH(CVA6Cfg.MEM_TID_WIDTH),
       .DEPTH     (MetaFifoDepth)
   ) i_wr_dcache_id (
       .clk_i     (clk_i),

core/cache_subsystem/wt_cache_subsystem.sv

@@ -88,10 +88,10 @@ module wt_cache_subsystem
     logic [2:0]                                      size;        // transaction size: 000=Byte 001=2Byte; 010=4Byte; 011=8Byte; 111=Cache line (16/32Byte)
     logic [L1D_WAY_WIDTH-1:0] way;  // way to replace
     logic [riscv::PLEN-1:0] paddr;  // physical address
-    riscv::xlen_t data;  // word width of processor (no block stores at the moment)
+    logic [riscv::XLEN-1:0] data;  // word width of processor (no block stores at the moment)
     logic [ariane_pkg::DATA_USER_WIDTH-1:0]          user;        // user width of processor (no block stores at the moment)
     logic nc;  // noncacheable
-    logic [CACHE_ID_WIDTH-1:0] tid;  // threadi id (used as transaction id in Ariane)
+    logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid;  // threadi id (used as transaction id in Ariane)
     ariane_pkg::amo_t amo_op;  // amo opcode
   };
 
@@ -100,7 +100,7 @@ module wt_cache_subsystem
     logic [ariane_pkg::DCACHE_LINE_WIDTH-1:0] data;  // full cache line width
     logic [ariane_pkg::DCACHE_USER_LINE_WIDTH-1:0] user;  // user bits
     dcache_inval_t inv;  // invalidation vector
-    logic [CACHE_ID_WIDTH-1:0] tid;  // threadi id (used as transaction id in Ariane)
+    logic [CVA6Cfg.MEM_TID_WIDTH-1:0] tid;  // threadi id (used as transaction id in Ariane)
   };
 
   logic icache_adapter_data_req, adapter_icache_data_ack, adapter_icache_rtrn_vld;