Update after parametrization changes (#1943)

docs/04_cv32a65x_design/source/parameters_cv32a65x.rst

@@ -16,6 +16,14 @@
      - description
      - Value
 
+   * - XLEN
+     - General Purpose Register Size (in bits)
+     - 32
+
+   * - FPGA_EN
+     - Is FPGA optimization of CV32A6
+     - 0
+
    * - NrCommitPorts
      - Number of commit ports
      - 1
@@ -80,6 +88,10 @@
      - Zcb RISC-V extension
      - 1
 
+   * - RVZCMP
+     - Zcmp RISC-V extension
+     - 0
+
    * - XFVec
      - Non standard Vector Floating Point
      - 0
@@ -100,6 +112,10 @@
      - User mode
      - 0
 
+   * - NrScoreboardEntries
+     - Scoreboard length
+     - 4
+
    * - HaltAddress
      - Address to jump when halt request
      - 64'h800
@@ -195,3 +211,39 @@
    * - AxiBurstWriteEn
      - AXI burst in write
      - 0
+
+   * - IcacheByteSize
+     - Instruction cache size (in bytes)
+     - 2048
+
+   * - IcacheSetAssoc
+     - Instruction cache associativity (number of ways)
+     - 2
+
+   * - IcacheLineWidth
+     - Instruction line width
+     - 128
+
+   * - DcacheByteSize
+     - Data cache size (in bytes)
+     - 32768
+
+   * - DcacheSetAssoc
+     - Data cache associativity (number of ways)
+     - 8
+
+   * - DcacheLineWidth
+     - Data line width
+     - 128
+
+   * - DataUserEn
+     - TODO
+     - 0
+
+   * - FetchUserWidth
+     - TODO
+     - 32
+
+   * - FetchUserEn
+     - TODO
+     - 0

docs/04_cv32a65x_design/source/port_alu.rst

@@ -40,7 +40,7 @@
      - out
      - ALU result
      - ISSUE_STAGE
-     - riscv::xlen_t
+     - logic[CVA6Cfg.XLEN-1:0]
 
    * - ``alu_branch_res_o``
      - out

docs/04_cv32a65x_design/source/port_bht.rst

@@ -34,7 +34,7 @@
      - in
      - Virtual PC
      - CACHE
-     - logic[riscv::VLEN-1:0]
+     - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``bht_update_i``
      - in
@@ -46,7 +46,7 @@
      - out
      - Prediction from bht
      - FRONTEND
-     - ariane_pkg::bht_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0]
+     - ariane_pkg::bht_prediction_t[CVA6Cfg.INSTR_PER_FETCH-1:0]
 
 Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
 

docs/04_cv32a65x_design/source/port_branch_unit.rst

@@ -40,7 +40,7 @@
      - in
      - Instruction PC
      - ISSUE_STAGE
-     - logic[riscv::VLEN-1:0]
+     - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``is_compressed_instr_i``
      - in
@@ -70,7 +70,7 @@
      - out
      - Brach unit result
      - ISSUE_STAGE
-     - logic[riscv::VLEN-1:0]
+     - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``branch_predict_i``
      - in

docs/04_cv32a65x_design/source/port_btb.rst

@@ -34,7 +34,7 @@
      - in
      - Virtual PC
      - CACHE
-     - logic[riscv::VLEN-1:0]
+     - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``btb_update_i``
      - in
@@ -46,7 +46,7 @@
      - out
      - BTB Prediction
      - FRONTEND
-     - btb_prediction_t[ariane_pkg::INSTR_PER_FETCH-1:0]
+     - btb_prediction_t[CVA6Cfg.INSTR_PER_FETCH-1:0]
 
 Due to cv32a65x configuration, some ports are tied to a static value. These ports do not appear in the above table, they are listed below
 

docs/04_cv32a65x_design/source/port_commit_stage.rst

@@ -60,6 +60,12 @@
      - ISSUE_STAGE
      - logic[CVA6Cfg.NrCommitPorts-1:0]
 
+   * - ``commit_macro_ack_o``
+     - out
+     - Acknowledge that we are indeed committing
+     - CSR_REGFILE
+     - logic[CVA6Cfg.NrCommitPorts-1:0]
+
    * - ``waddr_o``
      - out
      - Register file write address
@@ -70,7 +76,7 @@
      - out
      - Register file write data
      - ISSUE_STAGE
-     - logic[CVA6Cfg.NrCommitPorts-1:0][riscv::XLEN-1:0]
+     - logic[CVA6Cfg.NrCommitPorts-1:0][CVA6Cfg.XLEN-1:0]
 
    * - ``we_gpr_o``
      - out
@@ -88,7 +94,7 @@
      - out
      - TO_BE_COMPLETED
      - FRONTEND_CSR_REGFILE
-     - logic[riscv::VLEN-1:0]
+     - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``csr_op_o``
      - out
@@ -100,13 +106,13 @@
      - out
      - Data to write to CSR
      - CSR_REGFILE
-     - riscv::xlen_t
+     - logic[CVA6Cfg.XLEN-1:0]
 
    * - ``csr_rdata_i``
      - in
      - Data to read from CSR
      - CSR_REGFILE
-     - riscv::xlen_t
+     - logic[CVA6Cfg.XLEN-1:0]
 
    * - ``csr_exception_i``
      - in
@@ -130,7 +136,7 @@
      - out
      - Transaction id of first commit port
      - ID_STAGE
-     - logic[TRANS_ID_BITS-1:0]
+     - logic[CVA6Cfg.TRANS_ID_BITS-1:0]
 
    * - ``no_st_pending_i``
      - in

docs/04_cv32a65x_design/source/port_compressed_decoder.rst

@@ -36,6 +36,12 @@
      - decoder
      - logic
 
+   * - ``is_macro_instr_o``
+     - out
+     - Output instruction is macro
+     - decoder
+     - logic
+
    * - ``is_compressed_o``
      - out
      - Output instruction is compressed

docs/04_cv32a65x_design/source/port_csr_buffer.rst

@@ -58,7 +58,7 @@
      - out
      - CSR buffer result
      - ISSUE_STAGE
-     - riscv::xlen_t
+     - logic[CVA6Cfg.XLEN-1:0]
 
    * - ``csr_commit_i``
      - in

docs/04_cv32a65x_design/source/port_csr_regfile.rst

@@ -64,13 +64,13 @@
      - in
      - Address from which to start booting, mtvec is set to the same address
      - SUBSYSTEM
-     - logic[riscv::VLEN-1:0]
+     - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``hart_id_i``
      - in
      - Hart id in a multicore environment (reflected in a CSR)
      - SUBSYSTEM
-     - logic[riscv::XLEN-1:0]
+     - logic[CVA6Cfg.XLEN-1:0]
 
    * - ``ex_i``
      - in
@@ -94,19 +94,19 @@
      - in
      - Write data in
      - COMMIT_STAGE
-     - logic[riscv::XLEN-1:0]
+     - logic[CVA6Cfg.XLEN-1:0]
 
    * - ``csr_rdata_o``
      - out
      - Read data out
      - COMMIT_STAGE
-     - logic[riscv::XLEN-1:0]
+     - logic[CVA6Cfg.XLEN-1:0]
 
    * - ``pc_i``
      - in
      - PC of instruction accessing the CSR
      - COMMIT_STAGE
-     - logic[riscv::VLEN-1:0]
+     - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``csr_exception_o``
      - out
@@ -118,7 +118,7 @@
      - out
      - Output the exception PC to PC Gen, the correct CSR (mepc, sepc) is set accordingly
      - FRONTEND
-     - logic[riscv::VLEN-1:0]
+     - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``eret_o``
      - out
@@ -130,7 +130,7 @@
      - out
      - Output base of exception vector, correct CSR is output (mtvec, stvec)
      - FRONTEND
-     - logic[riscv::VLEN-1:0]
+     - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``irq_ctrl_o``
      - out

docs/04_cv32a65x_design/source/port_cva6.rst

@@ -34,13 +34,13 @@
      - in
      - Reset boot address
      - SUBSYSTEM
-     - logic[riscv::VLEN-1:0]
+     - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``hart_id_i``
      - in
      - Hard ID reflected as CSR
      - SUBSYSTEM
-     - logic[riscv::XLEN-1:0]
+     - logic[CVA6Cfg.XLEN-1:0]
 
    * - ``irq_i``
      - in

docs/04_cv32a65x_design/source/port_cva6_hpdcache_subsystem.rst

@@ -58,25 +58,25 @@
      - in
      - Input address translation request
      - EX_STAGE
-     - ariane_pkg::icache_areq_t
+     - icache_areq_t
 
    * - ``icache_areq_o``
      - out
      - Output address translation request
      - EX_STAGE
-     - ariane_pkg::icache_arsp_t
+     - icache_arsp_t
 
    * - ``icache_dreq_i``
      - in
      - Input data translation request
      - FRONTEND
-     - ariane_pkg::icache_dreq_t
+     - icache_dreq_t
 
    * - ``icache_dreq_o``
      - out
      - Output data translation request
      - FRONTEND
-     - ariane_pkg::icache_drsp_t
+     - icache_drsp_t
 
    * - ``dcache_enable_i``
      - in
@@ -112,13 +112,13 @@
      - in
      - Data cache input request ports
      - EX_STAGE
-     - ariane_pkg::dcache_req_i_t[NumPorts-1:0]
+     - dcache_req_i_t[NumPorts-1:0]
 
    * - ``dcache_req_ports_o``
      - out
      - Data cache output request ports
      - EX_STAGE
-     - ariane_pkg::dcache_req_o_t[NumPorts-1:0]
+     - dcache_req_o_t[NumPorts-1:0]
 
    * - ``wbuffer_empty_o``
      - out

docs/04_cv32a65x_design/source/port_cvxif_fu.rst

@@ -58,7 +58,7 @@
      - out
      - CVXIF transaction ID
      - ISSUE_STAGE
-     - logic[TRANS_ID_BITS-1:0]
+     - logic[CVA6Cfg.TRANS_ID_BITS-1:0]
 
    * - ``x_exception_o``
      - out
@@ -70,7 +70,7 @@
      - out
      - CVXIF FU result
      - ISSUE_STAGE
-     - riscv::xlen_t
+     - logic[CVA6Cfg.XLEN-1:0]
 
    * - ``x_valid_o``
      - out

docs/04_cv32a65x_design/source/port_decoder.rst

@@ -22,7 +22,7 @@
      - in
      - PC from fetch stage
      - FRONTEND
-     - logic[riscv::VLEN-1:0]
+     - logic[CVA6Cfg.VLEN-1:0]
 
    * - ``is_compressed_i``
      - in
@@ -48,6 +48,24 @@
      - FRONTEND
      - logic[31:0]
 
+   * - ``is_macro_instr_i``
+     - in
+     - Is a macro instruction
+     - macro_decoder
+     - logic
+
+   * - ``is_last_macro_instr_i``
+     - in
+     - Is a last macro instruction
+     - macro_decoder
+     - logic
+
+   * - ``is_double_rd_macro_instr_i``
+     - in
+     - Is mvsa01/mva01s macro instruction
+     - macro_decoder
+     - logic
+
    * - ``branch_predict_i``
      - in
      - Is a branch predict instruction