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cva6: Make xlen configurable (#459)
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This commit adds the possibility to configure cva6 to be a 32-bit processor,
saving significant area. Currently, the 32-bit version is preliminary, it does
not yet implement the entire privileged specification. Hence it does not allow
booting Linux yet.
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@JeanRochCoulon
JeanRochCoulon committed Sep 10, 2020
1 parent 3663eeb commit e2ff94d
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Showing 30 changed files with 484 additions and 473 deletions.
8 changes: 4 additions & 4 deletions bootrom/Makefile
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
bootrom_img = bootrom.img bootrom.sv

GCC=riscv64-unknown-elf-gcc
OBJCOPY=riscv64-unknown-elf-objcopy
RISCV_GCC?=riscv64-unknown-elf-gcc
RISCV_OBJCOPY?=riscv64-unknown-elf-objcopy
DTB=ariane.dtb
PYTHON=python

Expand All @@ -11,10 +11,10 @@ all: $(bootrom_img)
dd if=$< of=$@ bs=128

%.bin: %.elf
$(OBJCOPY) -O binary $< $@
$(RISCV_OBJCOPY) -O binary $< $@

%.elf: %.S linker.ld $(DTB)
$(GCC) -Tlinker.ld $< -nostdlib -static -Wl,--no-gc-sections -o $@
$(RISCV_GCC) -Tlinker.ld -march=rv32i -mabi=ilp32 $< -nostdlib -static -Wl,--no-gc-sections -o $@

%.dtb: %.dts
dtc -I dts $< -O dtb -o $@
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4 changes: 4 additions & 0 deletions bootrom/bootrom.S
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Original file line number Diff line number Diff line change
@@ -1,6 +1,10 @@
.section .text.start, "ax", @progbits
.globl _start
_start:
# bootrom.sv need to be functional in 64 and 32 bits,
# li s0, DRAM_BASE creates instructions not compatible with both
# versions. That's why we have replaced it by li and slli instructions
# to generates code compatible with both versions.
li s0, 1
slli s0, s0, 31
csrr a0, mhartid
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10 changes: 5 additions & 5 deletions bootrom/bootrom.h
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Expand Up @@ -3,12 +3,12 @@
const int reset_vec_size = 402;

uint32_t reset_vec[reset_vec_size] = {
0x047e4405,
0x00100413,
0x01f41413,
0xf1402573,
0x00000597,
0x07858593,
0x00008402,
0x00000000,
0x07458593,
0x00040067,
0x00000000,
0x00000000,
0x00000000,
Expand All @@ -23,7 +23,7 @@ uint32_t reset_vec[reset_vec_size] = {
0x00000597,
0x03c58593,
0x10500073,
0x0000bff5,
0xffdff06f,
0x00000000,
0x00000000,
0x00000000,
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Binary file modified bootrom/bootrom.img
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8 changes: 4 additions & 4 deletions bootrom/bootrom.sv
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Expand Up @@ -213,17 +213,17 @@ module bootrom (
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_0000bff5,
64'h00000000_ffdff06f,
64'h10500073_03c58593,
64'h00000597_f1402573,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00000000,
64'h00000000_00008402,
64'h07858593_00000597,
64'hf1402573_047e4405
64'h00040067_07458593,
64'h00000597_f1402573,
64'h01f41413_00100413
};

logic [$clog2(RomSize)-1:0] addr_q;
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69 changes: 34 additions & 35 deletions include/ariane_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -131,7 +131,7 @@ package ariane_pkg;
localparam NR_SB_ENTRIES = 8; // number of scoreboard entries
localparam TRANS_ID_BITS = $clog2(NR_SB_ENTRIES); // depending on the number of scoreboard entries we need that many bits
// to uniquely identify the entry in the scoreboard
localparam ASID_WIDTH = 16;
localparam ASID_WIDTH = (riscv::XLEN == 64) ? 16 : 1;
localparam BITS_SATURATION_COUNTER = 2;
localparam NR_COMMIT_PORTS = 2;

Expand All @@ -156,15 +156,14 @@ package ariane_pkg;
localparam int unsigned DEPTH_COMMIT = 8;
`endif


`ifdef PITON_ARIANE
// Floating-point extensions configuration
localparam bit RVF = 1'b1; // Is F extension enabled
localparam bit RVD = 1'b1; // Is D extension enabled
localparam bit RVF = riscv::IS_XLEN64; // Is F extension enabled
localparam bit RVD = riscv::IS_XLEN64; // Is D extension enabled
`else
// Floating-point extensions configuration
localparam bit RVF = 1'b1; // Is F extension enabled
localparam bit RVD = 1'b1; // Is D extension enabled
localparam bit RVF = riscv::IS_XLEN64; // Is F extension enabled
localparam bit RVD = riscv::IS_XLEN64; // Is D extension enabled
`endif
localparam bit RVA = 1'b1; // Is A extension enabled

Expand Down Expand Up @@ -205,9 +204,9 @@ package ariane_pkg;
// ^^^^ until here ^^^^
// ---------------------

localparam logic [63:0] ARIANE_MARCHID = 64'd3;
localparam riscv::xlen_t ARIANE_MARCHID = {{riscv::XLEN-32{1'b0}}, 32'd3};

localparam logic [63:0] ISA_CODE = (RVA << 0) // A - Atomic Instructions extension
localparam riscv::xlen_t ISA_CODE = (RVA << 0) // A - Atomic Instructions extension
| (1 << 2) // C - Compressed extension
| (RVD << 3) // D - Double precsision floating-point extension
| (RVF << 5) // F - Single precsision floating-point extension
Expand All @@ -217,7 +216,7 @@ package ariane_pkg;
| (1 << 18) // S - Supervisor mode implemented
| (1 << 20) // U - User mode implemented
| (NSX << 23) // X - Non-standard extensions present
| (1 << 63); // RV64
| ((riscv::XLEN == 64 ? 2 : 1) << riscv::XLEN-2); // MXL

// 32 registers + 1 bit for re-naming = 6
localparam REG_ADDR_SIZE = 6;
Expand Down Expand Up @@ -266,7 +265,7 @@ package ariane_pkg;
| riscv::SSTATUS_UPIE
| riscv::SSTATUS_SPIE
| riscv::SSTATUS_UXL
| riscv::SSTATUS64_SD;
| riscv::SSTATUS_SD;

localparam logic [63:0] SMODE_STATUS_WRITE_MASK = riscv::SSTATUS_SIE
| riscv::SSTATUS_SPIE
Expand All @@ -287,8 +286,8 @@ package ariane_pkg;
// Only use struct when signals have same direction
// exception
typedef struct packed {
logic [63:0] cause; // cause of exception
logic [63:0] tval; // additional information of causing exception (e.g.: instruction causing it),
riscv::xlen_t cause; // cause of exception
riscv::xlen_t tval; // additional information of causing exception (e.g.: instruction causing it),
// address of LD/ST fault
logic valid;
} exception_t;
Expand Down Expand Up @@ -369,9 +368,9 @@ package ariane_pkg;
// All information needed to determine whether we need to associate an interrupt
// with the corresponding instruction or not.
typedef struct packed {
logic [63:0] mie;
logic [63:0] mip;
logic [63:0] mideleg;
riscv::xlen_t mie;
riscv::xlen_t mip;
riscv::xlen_t mideleg;
logic sie;
logic global_enable;
} irq_ctrl_t;
Expand Down Expand Up @@ -475,9 +474,9 @@ package ariane_pkg;
typedef struct packed {
fu_t fu;
fu_op operator;
logic [63:0] operand_a;
logic [63:0] operand_b;
logic [63:0] imm;
riscv::xlen_t operand_a;
riscv::xlen_t operand_b;
riscv::xlen_t imm;
logic [TRANS_ID_BITS-1:0] trans_id;
} fu_data_t;

Expand Down Expand Up @@ -597,7 +596,7 @@ package ariane_pkg;
logic [REG_ADDR_SIZE-1:0] rs1; // register source address 1
logic [REG_ADDR_SIZE-1:0] rs2; // register source address 2
logic [REG_ADDR_SIZE-1:0] rd; // register destination address
logic [63:0] result; // for unfinished instructions this field also holds the immediate,
riscv::xlen_t result; // for unfinished instructions this field also holds the immediate,
// for unfinished floating-point that are partly encoded in rs2, this field also holds rs2
// for unfinished floating-point fused operations (FMADD, FMSUB, FNMADD, FNMSUB)
// this field holds the address of the third operand from the floating-point register file
Expand Down Expand Up @@ -640,9 +639,6 @@ package ariane_pkg;
riscv::pte_t content;
} tlb_update_t;

localparam logic [3:0] MODE_SV39 = 4'h8;
localparam logic [3:0] MODE_OFF = 4'h0;

// Bits required for representation of physical address space as 4K pages
// (e.g. 27*4K == 39bit address space).
localparam PPN4K_WIDTH = 38;
Expand Down Expand Up @@ -724,8 +720,8 @@ package ariane_pkg;
// ----------------------
// Arithmetic Functions
// ----------------------
function automatic logic [63:0] sext32 (logic [31:0] operand);
return {{32{operand[31]}}, operand[31:0]};
function automatic riscv::xlen_t sext32 (logic [31:0] operand);
return {{riscv::XLEN-32{operand[31]}}, operand[31:0]};
endfunction

// ----------------------
Expand All @@ -747,18 +743,21 @@ package ariane_pkg;
// LSU Functions
// ----------------------
// align data to address e.g.: shift data to be naturally 64
function automatic logic [63:0] data_align (logic [2:0] addr, logic [63:0] data);
case (addr)
3'b000: return data;
3'b001: return {data[55:0], data[63:56]};
3'b010: return {data[47:0], data[63:48]};
3'b011: return {data[39:0], data[63:40]};
3'b100: return {data[31:0], data[63:32]};
3'b101: return {data[23:0], data[63:24]};
3'b110: return {data[15:0], data[63:16]};
3'b111: return {data[7:0], data[63:8]};
function automatic riscv::xlen_t data_align (logic [2:0] addr, logic [63:0] data);
// Set addr[2] to 1'b0 when 32bits
logic [2:0] addr_tmp = {(addr[2] && riscv::IS_XLEN64), addr[1:0]};
logic [63:0] data_tmp = {64{1'b0}};
case (addr_tmp)
3'b000: data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-1:0]};
3'b001: data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-9:0], data[riscv::XLEN-1:riscv::XLEN-8]};
3'b010: data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-17:0], data[riscv::XLEN-1:riscv::XLEN-16]};
3'b011: data_tmp[riscv::XLEN-1:0] = {data[riscv::XLEN-25:0], data[riscv::XLEN-1:riscv::XLEN-24]};
3'b100: data_tmp = {data[31:0], data[63:32]};
3'b101: data_tmp = {data[23:0], data[63:24]};
3'b110: data_tmp = {data[15:0], data[63:16]};
3'b111: data_tmp = {data[7:0], data[63:8]};
endcase
return data;
return data_tmp[riscv::XLEN-1:0];
endfunction

// generate byte enable mask
Expand Down

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