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8331577: RISC-V: C2 CountLeadingZerosV
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8331578: RISC-V: C2 CountTrailingZerosV

Reviewed-by: fyang
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Hamlin Li committed May 10, 2024
1 parent 675fbe6 commit f95c937
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Showing 3 changed files with 72 additions and 10 deletions.
3 changes: 3 additions & 0 deletions src/hotspot/cpu/riscv/assembler_riscv.hpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1891,6 +1891,9 @@ enum Nf {
INSN(vbrev8_v, 0b1010111, 0b010, 0b01000, 0b010010); // reverse bits in every byte of element
INSN(vrev8_v, 0b1010111, 0b010, 0b01001, 0b010010); // reverse bytes in every elememt

INSN(vclz_v, 0b1010111, 0b010, 0b01100, 0b010010); // count leading zeros
INSN(vctz_v, 0b1010111, 0b010, 0b01101, 0b010010); // count trailing zeros

#undef INSN

#define INSN(NAME, op, funct3, vm, funct6) \
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76 changes: 67 additions & 9 deletions src/hotspot/cpu/riscv/riscv_v.ad
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Expand Up @@ -73,6 +73,8 @@ source %{
return false;
}
break;
case Op_CountTrailingZerosV:
case Op_CountLeadingZerosV:
case Op_ReverseBytesV:
case Op_PopCountVL:
case Op_PopCountVI:
Expand Down Expand Up @@ -3759,14 +3761,14 @@ instruct vsignum_reg(vReg dst, vReg zero, vReg one, vRegMask_V0 v0) %{

// -------------------------------- Reverse Bytes Vector Operations ------------------------

instruct vreverse_bytes_masked(vReg dst, vReg src, vRegMask_V0 v0) %{
match(Set dst (ReverseBytesV src v0));
format %{ "vreverse_bytes_masked $dst, $src, v0" %}
instruct vreverse_bytes_masked(vReg dst_src, vRegMask_V0 v0) %{
match(Set dst_src (ReverseBytesV dst_src v0));
format %{ "vreverse_bytes_masked $dst_src, $dst_src, v0" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vrev8_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), Assembler::v0_t);
__ vrev8_v(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}
Expand Down Expand Up @@ -3817,16 +3819,16 @@ instruct vconvF2HF(vReg dst, vReg src, vReg vtmp, vRegMask_V0 v0, iRegINoSp tmp)

// ------------------------------ Popcount vector ------------------------------

instruct vpopcount_masked(vReg dst, vReg src, vRegMask_V0 v0) %{
match(Set dst (PopCountVI src v0));
match(Set dst (PopCountVL src v0));
instruct vpopcount_masked(vReg dst_src, vRegMask_V0 v0) %{
match(Set dst_src (PopCountVI dst_src v0));
match(Set dst_src (PopCountVL dst_src v0));
ins_cost(VEC_COST);
format %{ "vcpop_v $dst, $src, $v0\t# vcpop_v with mask" %}
format %{ "vcpop_v $dst_src, $dst_src, $v0\t# vcpop_v with mask" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vcpop_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg), Assembler::v0_t);
__ vcpop_v(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}
Expand All @@ -3845,6 +3847,62 @@ instruct vpopcount(vReg dst, vReg src) %{
ins_pipe(pipe_slow);
%}

// ------------------------------ CountLeadingZerosV --------------------------

instruct vcountLeadingZeros_masked(vReg dst_src, vRegMask_V0 v0) %{
match(Set dst_src (CountLeadingZerosV dst_src v0));
ins_cost(VEC_COST);
format %{ "vcount_leading_zeros_masked $dst_src, $dst_src, v0" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vclz_v(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}

instruct vcountLeadingZeros(vReg dst, vReg src) %{
match(Set dst (CountLeadingZerosV src));
ins_cost(VEC_COST);
format %{ "vcount_leading_zeros $dst, $src" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vclz_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}

// ------------------------------ CountTrailingZerosV --------------------------

instruct vcountTrailingZeros_masked(vReg dst_src, vRegMask_V0 v0) %{
match(Set dst_src (CountTrailingZerosV dst_src v0));
ins_cost(VEC_COST);
format %{ "vcount_trailing_zeros_masked $dst_src, $dst_src, v0" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vctz_v(as_VectorRegister($dst_src$$reg), as_VectorRegister($dst_src$$reg), Assembler::v0_t);
%}
ins_pipe(pipe_slow);
%}

instruct vcountTrailingZeros(vReg dst, vReg src) %{
match(Set dst (CountTrailingZerosV src));
ins_cost(VEC_COST);
format %{ "vcount_trailing_zeros $dst, $src" %}
ins_encode %{
BasicType bt = Matcher::vector_element_basic_type(this);
uint vlen = Matcher::vector_length(this);
__ vsetvli_helper(bt, vlen);
__ vctz_v(as_VectorRegister($dst$$reg), as_VectorRegister($src$$reg));
%}
ins_pipe(pipe_slow);
%}

// ------------------------------ Vector Load Gather ---------------------------

instruct gather_load(vReg dst, indirect mem, vReg idx) %{
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3 changes: 2 additions & 1 deletion test/hotspot/jtreg/compiler/vectorization/TestNumberOfContinuousZeros.java
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Original file line number Diff line number Diff line change
Expand Up @@ -27,7 +27,8 @@
* @summary Test vectorization of numberOfTrailingZeros/numberOfLeadingZeros for Long
* @requires vm.compiler2.enabled
* @requires (os.simpleArch == "x64" & vm.cpu.features ~= ".*avx2.*") |
* (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*sve.*")
* (os.simpleArch == "aarch64" & vm.cpu.features ~= ".*sve.*") |
* (os.simpleArch == "riscv64" & vm.cpu.features ~= ".*zvbb.*")
* @library /test/lib /
* @run driver compiler.vectorization.TestNumberOfContinuousZeros
*/
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