Add OHDL headers.

This is is a license which can be changed to GPL etc. as desired.
openrisc · Aug 21, 2012 · 2528046 · 2528046
1 parent 08c40e3
commit 2528046
Show file tree

Hide file tree

Showing 23 changed files with 385 additions and 190 deletions.
diff --git a/rtl/verilog/mor1kx-defines.v b/rtl/verilog/mor1kx-defines.v
@@ -1,7 +1,16 @@
-/*
- * mor1kx defines file
- * 
- * */
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+
+  Description: mor1kx defines
+   
+  Copyright (C) 2012 Authors
+ 
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
+ 
+***************************************************************************** */
 
 /* ORBIS32 opcodes - top 6 bits */
 

diff --git a/rtl/verilog/mor1kx-sprs.v b/rtl/verilog/mor1kx-sprs.v
@@ -1,8 +1,16 @@
-/*
- *
- * SPR definitions
- * 
- */
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+
+  Description: SPR definitions
+  
+  Copyright (C) 2012 Authors
+ 
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
+ 
+***************************************************************************** */
 
 //
 // Addresses

diff --git a/rtl/verilog/mor1kx.v b/rtl/verilog/mor1kx.v
@@ -1,6 +1,17 @@
-/*
- mor1kx processor top level
- */
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+
+  Description: mor1kx processor top level
+  
+  Copyright (C) 2012 Authors
+ 
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
+             Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
+ 
+***************************************************************************** */
 
 `include "mor1kx-defines.v"
 

diff --git a/rtl/verilog/mor1kx_bus_if_wb32.v b/rtl/verilog/mor1kx_bus_if_wb32.v
@@ -1,11 +1,18 @@
-/*
- mor1kx processor Wishbone bus bridge
- 
- For now, very simple, not registering
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+
+  Description: mor1kx processor Wishbone bus bridge
+  
+  For now, very simple, not registering,  assumes 32-bit data, addressing
+
+  Copyright (C) 2012 Authors
  
- assumes 32-bit data, addressing
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
  
- */
+***************************************************************************** */
 
 `include "mor1kx-defines.v"
 

diff --git a/rtl/verilog/mor1kx_cpu.v b/rtl/verilog/mor1kx_cpu.v
@@ -1,3 +1,20 @@
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+
+  Description: CPU wrapper module
+ 
+  Allows selection of CPU pipeline implementation based on parameter.
+ 
+  Also provides some API-like hooks into the pipeline for monitors.
+  
+  Copyright (C) 2012 Authors
+ 
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
+ 
+***************************************************************************** */
 
 `include "mor1kx-defines.v"
 

diff --git a/rtl/verilog/mor1kx_cpu_espresso.v b/rtl/verilog/mor1kx_cpu_espresso.v
@@ -1,3 +1,16 @@
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+
+  Description: Espresso pipeline CPU module
+  
+  Copyright (C) 2012 Authors
+ 
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
+ 
+***************************************************************************** */
 
 `include "mor1kx-defines.v"
 

diff --git a/rtl/verilog/mor1kx_cpu_fourstage.v b/rtl/verilog/mor1kx_cpu_fourstage.v
@@ -1,3 +1,16 @@
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+
+  Description: "Fourstage" pipeline CPU module
+  
+  Copyright (C) 2012 Authors
+ 
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
+ 
+***************************************************************************** */
 
 `include "mor1kx-defines.v"
 

diff --git a/rtl/verilog/mor1kx_ctrl_branch_fourstage.v b/rtl/verilog/mor1kx_ctrl_branch_fourstage.v
@@ -1,17 +1,29 @@
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+
+  Description: mor1k branch control
+
+  jump/branch address and opcode input from execute stage
+  
+  flag input from control stage
+  
+  branch indication from control stage
+  
+  generate branch occurred and new address for fetch stage
+  
+  wholly combinatorial for now
+  
+  Copyright (C) 2012 Authors
+ 
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
+ 
+***************************************************************************** */
 
 /*
  *
- * mor1k branch control
- * 
- * jump/branch address and opcode input from execute stage
- * 
- * flag input from control stage
- * 
- * branch indication from control stage
- * 
- * generate branch occurred and new address for fetch stage
- * 
- * wholly combinatorial for now
  * 
  */
 

diff --git a/rtl/verilog/mor1kx_ctrl_espresso.v b/rtl/verilog/mor1kx_ctrl_espresso.v
@@ -1,22 +1,29 @@
-
-/*
- * mor1k espresso pipeline control unit
- * 
- * inputs from execute stage
- * 
- * generate pipeline controls
- * 
- * manage SPRs
- * 
- * issue addresses for exceptions to fetch stage
- * control branches going to fetch stage
- * 
- * contains tick timer
- * 
- * contains PIC logic
- * 
- */
-
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+
+  Description: mor1kx espresso pipeline control unit		  
+ 						  
+  inputs from execute stage			  
+ 						  
+  generate pipeline controls			  
+ 						  
+  manage SPRs					  
+ 						  
+  issue addresses for exceptions to fetch stage  
+  control branches going to fetch stage	  
+ 						  
+  contains tick timer				  
+ 						  
+  contains PIC logic                             
+   
+  Copyright (C) 2012 Authors
+ 
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
+ 
+***************************************************************************** */
 
 `include "mor1kx-defines.v"
 

diff --git a/rtl/verilog/mor1kx_ctrl_fourstage.v b/rtl/verilog/mor1kx_ctrl_fourstage.v
@@ -1,33 +1,39 @@
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
 
-/*
- * mor1k control unit
- * 
- * inputs from execute stage
- * 
- * generate pipeline controls
- * 
- * manage SPRs
- * 
- * issue addresses for exceptions to fetch stage
- * control branches going to fetch stage
- * 
- * contains tick timer
- * 
- * contains PIC logic
- * 
- * 
- * l.mfspr implemented as follows:
- * We receieve an indication from the execute stage if it has a l.mfspr 
- * instruction. We take note of this and it causes a 1-cycle stall of
- * the fetch and decode stages. We still issue the asserted padv_execute so
- * we get the result from the ALU which will be the address of the SPR to write
- * into the register file. On the next cycle, with the SPR address known, the
- * data is output to the RF and the ctrl_mfspr_we_o is asserted ensuring this 
- * value is written into the RF. As we introduced a delay in the fetch/decode
- * logic, this should not clash with the next instruction to be executed.
- * 
- */
-
+  Description: mor1k control unit
+   
+  inputs from execute stage
+  
+  generate pipeline controls
+  
+  manage SPRs
+  
+  issue addresses for exceptions to fetch stage
+  control branches going to fetch stage
+  
+  contains tick timer
+  
+  contains PIC logic
+  
+  l.mfspr implemented as follows:
+  We receieve an indication from the execute stage if it has a l.mfspr 
+  instruction. We take note of this and it causes a 1-cycle stall of
+  the fetch and decode stages. We still issue the asserted padv_execute so
+  we get the result from the ALU which will be the address of the SPR to write
+  into the register file. On the next cycle, with the SPR address known, the
+  data is output to the RF and the ctrl_mfspr_we_o is asserted ensuring this 
+  value is written into the RF. As we introduced a delay in the fetch/decode
+  logic, this should not clash with the next instruction to be executed.
+   
+  Copyright (C) 2012 Authors
+ 
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
+ 
+***************************************************************************** */
 
 `include "mor1kx-defines.v"
 

diff --git a/rtl/verilog/mor1kx_dcache.v b/rtl/verilog/mor1kx_dcache.v
@@ -1,6 +1,7 @@
 /*
  * (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
  */
+
 `include "mor1kx-defines.v"
 
 module mor1kx_dcache

diff --git a/rtl/verilog/mor1kx_decode.v b/rtl/verilog/mor1kx_decode.v
@@ -1,15 +1,23 @@
-/*
- * mor1kx decode unit
- * 
- * Outputs:
- *  - ALU operation
- *  - indication of other type of op - LSU/SPR
- *  - immediates
- *  - register file addresses
- *  - exception decodes:  illegal, system call
- * 
- * 
- * */
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+
+  Description: mor1kx decode unit
+  
+  Outputs:
+   - ALU operation
+   - indication of other type of op - LSU/SPR
+   - immediates
+   - register file addresses
+   - exception decodes:  illegal, system call
+   
+  Copyright (C) 2012 Authors
+ 
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
+ 
+***************************************************************************** */
 
 `include "mor1kx-defines.v"
 

diff --git a/rtl/verilog/mor1kx_execute_alu.v b/rtl/verilog/mor1kx_execute_alu.v
@@ -1,12 +1,19 @@
-/*
- * ALU
- * 
- * inputs are opcodes, the immediate field, operands from RF, instruction 
- * opcode
- * 
- * TODO -
- * serial multiplier
- */
+/* ****************************************************************************
+  This Source Code Form is subject to the terms of the 
+  Open Hardware Description License, v. 1.0. If a copy 
+  of the OHDL was not distributed with this file, You 
+  can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
+
+  Description: mor1kx execute stage ALU
+   
+  Inputs are opcodes, the immediate field, operands from RF, instruction 
+  opcode
+ 
+  Copyright (C) 2012 Authors
+ 
+  Author(s): Julius Baxter <juliusbaxter@gmail.com>
+ 
+***************************************************************************** */
 
 `include "mor1kx-defines.v"