You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
It is a regression introduced by d6d5529 . Just an orphaned bracket
Error (10170): Verilog HDL syntax error at orpsoc_top.v(915) near text: ")"; mismatched closing parenthesis . Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v Line: 915
Error (10170): Verilog HDL syntax error at orpsoc_top.v(915) near text: ")"; expecting "(". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Altera Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. File: /fusesoc/build/sockit/src/sockit/rtl/verilog/orpsoc_top.v Line: 915
The text was updated successfully, but these errors were encountered:
oleg-nenashev
added a commit
to oleg-nenashev/orpsoc-cores
that referenced
this issue
Sep 8, 2016
It is a regression introduced by d6d5529 . Just an orphaned bracket
The text was updated successfully, but these errors were encountered: