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uboot-ramips: add support for MT7621, merge into uboot-mediatek
* Merge uboot-ramips into uboot-mediatek. * Port support for the RAVPower RP WD009 to U-Boot 2022.07. * Add support for MT7621 and add builds for the reference boards. * Add builds for MT7620 and MT7628 reference boards. This should help to make development of U-Boot-level board support for all MediaTek targets much easier. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
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...ot-mediatek/patches/001-mtk-0001-mips-add-asm-mipsmtregs.h-for-MIPS-multi-threading.patch
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From 65a4a80157bacde3cf86ce8cbc9a08f5f05ad9bb Mon Sep 17 00:00:00 2001 | ||
From: Weijie Gao <weijie.gao@mediatek.com> | ||
Date: Fri, 20 May 2022 11:21:34 +0800 | ||
Subject: [PATCH 01/25] mips: add asm/mipsmtregs.h for MIPS multi-threading | ||
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To be compatible with old u-boot used by lots of MT7621 devices, the u-boot | ||
needs to boot-up MT7621's all cores, and all VPES of each core. | ||
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This patch adds asm/mipsmtregs.h from linux kernel which is need for | ||
boot-up VPEs. | ||
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Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> | ||
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> | ||
--- | ||
arch/mips/include/asm/mipsmtregs.h | 142 +++++++++++++++++++++++++++++ | ||
1 file changed, 142 insertions(+) | ||
create mode 100644 arch/mips/include/asm/mipsmtregs.h | ||
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diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h | ||
new file mode 100644 | ||
index 0000000000..ba82e2bd97 | ||
--- /dev/null | ||
+++ b/arch/mips/include/asm/mipsmtregs.h | ||
@@ -0,0 +1,142 @@ | ||
+/* SPDX-License-Identifier: GPL-2.0 */ | ||
+/* | ||
+ * MT regs definitions, follows on from mipsregs.h | ||
+ * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved. | ||
+ * Elizabeth Clarke et. al. | ||
+ * | ||
+ */ | ||
+#ifndef _ASM_MIPSMTREGS_H | ||
+#define _ASM_MIPSMTREGS_H | ||
+ | ||
+#include <asm/mipsregs.h> | ||
+ | ||
+/* | ||
+ * Macros for use in assembly language code | ||
+ */ | ||
+ | ||
+#define CP0_MVPCONTROL $0, 1 | ||
+#define CP0_MVPCONF0 $0, 2 | ||
+#define CP0_MVPCONF1 $0, 3 | ||
+#define CP0_VPECONTROL $1, 1 | ||
+#define CP0_VPECONF0 $1, 2 | ||
+#define CP0_VPECONF1 $1, 3 | ||
+#define CP0_YQMASK $1, 4 | ||
+#define CP0_VPESCHEDULE $1, 5 | ||
+#define CP0_VPESCHEFBK $1, 6 | ||
+#define CP0_TCSTATUS $2, 1 | ||
+#define CP0_TCBIND $2, 2 | ||
+#define CP0_TCRESTART $2, 3 | ||
+#define CP0_TCHALT $2, 4 | ||
+#define CP0_TCCONTEXT $2, 5 | ||
+#define CP0_TCSCHEDULE $2, 6 | ||
+#define CP0_TCSCHEFBK $2, 7 | ||
+#define CP0_SRSCONF0 $6, 1 | ||
+#define CP0_SRSCONF1 $6, 2 | ||
+#define CP0_SRSCONF2 $6, 3 | ||
+#define CP0_SRSCONF3 $6, 4 | ||
+#define CP0_SRSCONF4 $6, 5 | ||
+ | ||
+/* MVPControl fields */ | ||
+#define MVPCONTROL_EVP (_ULCAST_(1)) | ||
+ | ||
+#define MVPCONTROL_VPC_SHIFT 1 | ||
+#define MVPCONTROL_VPC (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT) | ||
+ | ||
+#define MVPCONTROL_STLB_SHIFT 2 | ||
+#define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT) | ||
+ | ||
+/* MVPConf0 fields */ | ||
+#define MVPCONF0_PTC_SHIFT 0 | ||
+#define MVPCONF0_PTC (_ULCAST_(0xff)) | ||
+#define MVPCONF0_PVPE_SHIFT 10 | ||
+#define MVPCONF0_PVPE (_ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT) | ||
+#define MVPCONF0_TCA_SHIFT 15 | ||
+#define MVPCONF0_TCA (_ULCAST_(1) << MVPCONF0_TCA_SHIFT) | ||
+#define MVPCONF0_PTLBE_SHIFT 16 | ||
+#define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT) | ||
+#define MVPCONF0_TLBS_SHIFT 29 | ||
+#define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT) | ||
+#define MVPCONF0_M_SHIFT 31 | ||
+#define MVPCONF0_M (_ULCAST_(0x1) << MVPCONF0_M_SHIFT) | ||
+ | ||
+/* config3 fields */ | ||
+#define CONFIG3_MT_SHIFT 2 | ||
+#define CONFIG3_MT (_ULCAST_(1) << CONFIG3_MT_SHIFT) | ||
+ | ||
+/* VPEControl fields (per VPE) */ | ||
+#define VPECONTROL_TARGTC (_ULCAST_(0xff)) | ||
+ | ||
+#define VPECONTROL_TE_SHIFT 15 | ||
+#define VPECONTROL_TE (_ULCAST_(1) << VPECONTROL_TE_SHIFT) | ||
+#define VPECONTROL_EXCPT_SHIFT 16 | ||
+#define VPECONTROL_EXCPT (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT) | ||
+ | ||
+/* Thread Exception Codes for EXCPT field */ | ||
+#define THREX_TU 0 | ||
+#define THREX_TO 1 | ||
+#define THREX_IYQ 2 | ||
+#define THREX_GSX 3 | ||
+#define THREX_YSCH 4 | ||
+#define THREX_GSSCH 5 | ||
+ | ||
+#define VPECONTROL_GSI_SHIFT 20 | ||
+#define VPECONTROL_GSI (_ULCAST_(1) << VPECONTROL_GSI_SHIFT) | ||
+#define VPECONTROL_YSI_SHIFT 21 | ||
+#define VPECONTROL_YSI (_ULCAST_(1) << VPECONTROL_YSI_SHIFT) | ||
+ | ||
+/* VPEConf0 fields (per VPE) */ | ||
+#define VPECONF0_VPA_SHIFT 0 | ||
+#define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT) | ||
+#define VPECONF0_MVP_SHIFT 1 | ||
+#define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT) | ||
+#define VPECONF0_XTC_SHIFT 21 | ||
+#define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) | ||
+ | ||
+/* VPEConf1 fields (per VPE) */ | ||
+#define VPECONF1_NCP1_SHIFT 0 | ||
+#define VPECONF1_NCP1 (_ULCAST_(0xff) << VPECONF1_NCP1_SHIFT) | ||
+#define VPECONF1_NCP2_SHIFT 10 | ||
+#define VPECONF1_NCP2 (_ULCAST_(0xff) << VPECONF1_NCP2_SHIFT) | ||
+#define VPECONF1_NCX_SHIFT 20 | ||
+#define VPECONF1_NCX (_ULCAST_(0xff) << VPECONF1_NCX_SHIFT) | ||
+ | ||
+/* TCStatus fields (per TC) */ | ||
+#define TCSTATUS_TASID (_ULCAST_(0xff)) | ||
+#define TCSTATUS_IXMT_SHIFT 10 | ||
+#define TCSTATUS_IXMT (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT) | ||
+#define TCSTATUS_TKSU_SHIFT 11 | ||
+#define TCSTATUS_TKSU (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT) | ||
+#define TCSTATUS_A_SHIFT 13 | ||
+#define TCSTATUS_A (_ULCAST_(1) << TCSTATUS_A_SHIFT) | ||
+#define TCSTATUS_DA_SHIFT 15 | ||
+#define TCSTATUS_DA (_ULCAST_(1) << TCSTATUS_DA_SHIFT) | ||
+#define TCSTATUS_DT_SHIFT 20 | ||
+#define TCSTATUS_DT (_ULCAST_(1) << TCSTATUS_DT_SHIFT) | ||
+#define TCSTATUS_TDS_SHIFT 21 | ||
+#define TCSTATUS_TDS (_ULCAST_(1) << TCSTATUS_TDS_SHIFT) | ||
+#define TCSTATUS_TSST_SHIFT 22 | ||
+#define TCSTATUS_TSST (_ULCAST_(1) << TCSTATUS_TSST_SHIFT) | ||
+#define TCSTATUS_RNST_SHIFT 23 | ||
+#define TCSTATUS_RNST (_ULCAST_(3) << TCSTATUS_RNST_SHIFT) | ||
+/* Codes for RNST */ | ||
+#define TC_RUNNING 0 | ||
+#define TC_WAITING 1 | ||
+#define TC_YIELDING 2 | ||
+#define TC_GATED 3 | ||
+ | ||
+#define TCSTATUS_TMX_SHIFT 27 | ||
+#define TCSTATUS_TMX (_ULCAST_(1) << TCSTATUS_TMX_SHIFT) | ||
+/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */ | ||
+ | ||
+/* TCBind */ | ||
+#define TCBIND_CURVPE_SHIFT 0 | ||
+#define TCBIND_CURVPE (_ULCAST_(0xf)) | ||
+ | ||
+#define TCBIND_CURTC_SHIFT 21 | ||
+ | ||
+#define TCBIND_CURTC (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT) | ||
+ | ||
+/* TCHalt */ | ||
+#define TCHALT_H (_ULCAST_(1)) | ||
+ | ||
+#endif | ||
-- | ||
2.36.1 | ||
|
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@dangowrt out of curiosity, will this be used by something in the near future?
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The reason why I picked the MT7621 patches is mostly that they were accepted into upstream U-Boot just after the 2022.07 release. Now that I'm working on U-Boot support for FiLogic MT7986 (see my stating tree) that was a precondition, because of course patches submitted to upstream are based on top of that (eg. the Ethernet driver). Also there were lots of people asking me if U-Boot level support for boards with particularly annoying vendor loaders is possible for boards other than the popular E8450/RT3200, and most of those are MT7621 based. Also the existing uboot-ramips was very outdated, merging it into uboot-mediatek (sharing many drivers) will make future maintainance easier (I'll take care of that).
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OK. I have one such router (RT1800) which is mostly why I was asking.
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Does the RT1800 come with parallel NAND or also SPI-NAND like the RT3200? Because afaik for SPI-NAND you need a special preloader (see https://github.com/hackpascal/mt7621-boot-spi-nand) on the MT7621 SoC which doesn't have native support for SPI-NAND in it's ROM loader...
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I haven't looked at it yet. It arrived today. It should be a variant of the E7350: #4470
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Ah ok, that looks like parallel NAND, so yes, you can use generate a loader for that board using the uboot-mediatek package now.