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Revert "ramips: improve interrupt mapping"
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This reverts commit 5f7396e.

Signed-off-by: John Crispin <john@phrozen.org>
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@blogic
blogic committed Jun 1, 2018
1 parent b9555a9 commit 82cfec0
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Showing 2 changed files with 69 additions and 14 deletions.
9 changes: 4 additions & 5 deletions target/linux/ramips/dts/mt7621.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -440,11 +440,10 @@
0x01000000 0 0x00000000 0x1e160000 0 0x00010000 /* io space */
>;

#interrupt-cells = <1>;
interrupt-map-mask = <0xF0000 0 0 1>;
interrupt-map = <0x10000 0 0 1 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
<0x20000 0 0 1 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
<0x30000 0 0 1 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;

status = "disabled";

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74 changes: 65 additions & 9 deletions target/linux/ramips/files-4.14/arch/mips/pci/pci-mt7621.c
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Original file line number Diff line number Diff line change
Expand Up @@ -74,6 +74,9 @@ extern void chk_phy_pll(void);

#define RALINK_PCI_CONFIG_ADDR 0x20
#define RALINK_PCI_CONFIG_DATA_VIRTUAL_REG 0x24
#define RALINK_INT_PCIE0 pcie_irq[0]
#define RALINK_INT_PCIE1 pcie_irq[1]
#define RALINK_INT_PCIE2 pcie_irq[2]
#define RALINK_PCI_MEMBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x0028)
#define RALINK_PCI_IOBASE *(volatile u32 *)(RALINK_PCI_BASE + 0x002C)
#define RALINK_PCIE0_RST (1<<24)
Expand Down Expand Up @@ -364,22 +367,75 @@ pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
u16 cmd;
u32 val;
int irq;

if (dev->bus->number == 0) {
write_config(0, slot, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, slot, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot %d = %x\n", slot, val);
int irq = 0;

if ((dev->bus->number == 0) && (slot == 0)) {
write_config(0, 0, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 0, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 0 = %x\n", val);
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
} else if((dev->bus->number == 0) && (slot == 0x1)) {
write_config(0, 1, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 1, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 1 = %x\n", val);
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
} else if((dev->bus->number == 0) && (slot == 0x2)) {
write_config(0, 2, 0, PCI_BASE_ADDRESS_0, MEMORY_BASE);
read_config(0, 2, 0, PCI_BASE_ADDRESS_0, (unsigned long *)&val);
printk("BAR0 at slot 2 = %x\n", val);
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
} else if ((dev->bus->number == 1) && (slot == 0x0)) {
switch (pcie_link_status) {
case 2:
case 6:
irq = RALINK_INT_PCIE1;
break;
case 4:
irq = RALINK_INT_PCIE2;
break;
default:
irq = RALINK_INT_PCIE0;
}
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number == 2) && (slot == 0x0)) {
switch (pcie_link_status) {
case 5:
case 6:
irq = RALINK_INT_PCIE2;
break;
default:
irq = RALINK_INT_PCIE1;
}
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number == 2) && (slot == 0x1)) {
switch (pcie_link_status) {
case 5:
case 6:
irq = RALINK_INT_PCIE2;
break;
default:
irq = RALINK_INT_PCIE1;
}
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x0)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x1)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else if ((dev->bus->number ==3) && (slot == 0x2)) {
irq = RALINK_INT_PCIE2;
printk("bus=0x%x, slot = 0x%x, irq=0x%x\n",dev->bus->number, slot, dev->irq);
} else {
printk("bus=0x%x, slot = 0x%x\n",dev->bus->number, slot);
return 0;
}

pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14); //configure cache line size 0x14
pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xFF); //configure latency timer 0x10
pci_read_config_word(dev, PCI_COMMAND, &cmd);
cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
pci_write_config_word(dev, PCI_COMMAND, cmd);

irq = of_irq_parse_and_map_pci(dev, slot, pin);

pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
return irq;
}
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