Remove fusesoc system files

These files are deprecated with fusesoc 1.6, as discussed here: https://github.com/olofk/fusesoc/blob/master/doc/migrations.adoc
optimsoc · Apr 11, 2017 · a2a30e8 · a2a30e8
1 parent 6cacc93
commit a2a30e8
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Showing 7 changed files with 23 additions and 33 deletions.
diff --git a/examples/fpga/nexys4ddr/compute_tile/compute_tile_nexys4ddr.core b/examples/fpga/nexys4ddr/compute_tile/compute_tile_nexys4ddr.core
@@ -14,6 +14,7 @@ depend =
   optimsoc:base:config
 
 simulators = xsim
+backend = vivado
 
 [fileset rtl_files]
 file_type = systemVerilogSource
@@ -31,6 +32,10 @@ files =
 top_module = tb_compute_tile_nexys4ddr
 part = xc7a100tcsg324-1
 
+[vivado]
+part = "xc7a100tcsg324-1"
+hw_device = xc7a100t_0
+
 [parameter NUM_CORES]
 datatype = int
 paramtype = vlogparam

diff --git a/examples/fpga/nexys4ddr/system_2x2_cccc/system_2x2_cccc_nexys4ddr.core b/examples/fpga/nexys4ddr/system_2x2_cccc/system_2x2_cccc_nexys4ddr.core
@@ -13,6 +13,7 @@ depend =
   optimsoc:ip:xilinx_axi_register_slice
 
 simulators = xsim
+backend = vivado
 
 [fileset rtl_files]
 file_type = systemVerilogSource
@@ -30,6 +31,10 @@ files =
 top_module = tb_system_2x2_cccc_nexys4ddr
 part = xc7a100tcsg324-1
 
+[vivado]
+part = "xc7a100tcsg324-1"
+hw_device = xc7a100t_0
+
 [parameter NUM_CORES]
 datatype = int
 paramtype = vlogparam

diff --git a/examples/fpga/nexys4ddr/system_2x2_cccc/system_2x2_cccc_nexys4ddr.system b/examples/fpga/nexys4ddr/system_2x2_cccc/system_2x2_cccc_nexys4ddr.system
diff --git a/examples/fpga/vcu108/compute_tile/compute_tile_vcu108.core b/examples/fpga/vcu108/compute_tile/compute_tile_vcu108.core
@@ -13,14 +13,18 @@ depend =
   glip:backend:uart
   optimsoc:base:config
 
-simulators = xsim
+backend = vivado
 
 [fileset rtl_files]
 file_type = systemVerilogSource
-usage = sim synth
+usage = synth
 files =
   rtl/verilog/compute_tile_dm_vcu108.sv
 
+[vivado]
+part = "xcvu095-ffva2104-2-e"
+hw_device = xcvu095_0
+
 [parameter NUM_CORES]
 datatype = int
 paramtype = vlogparam

diff --git a/examples/fpga/vcu108/compute_tile/compute_tile_vcu108.system b/examples/fpga/vcu108/compute_tile/compute_tile_vcu108.system
diff --git a/examples/fpga/vcu108/system_2x2_cccc/system_2x2_cccc_vcu108.core b/examples/fpga/vcu108/system_2x2_cccc/system_2x2_cccc_vcu108.core
@@ -13,12 +13,18 @@ depend =
   optimsoc:ip:xilinx_axi_register_slice
   optimsoc:base:config
 
+backend = vivado
+
 [fileset rtl_files]
 file_type = systemVerilogSource
-usage = sim synth
+usage = synth
 files =
   rtl/verilog/system_2x2_cccc_vcu108.sv
 
+[vivado]
+part = "xcvu095-ffva2104-2-e"
+hw_device = xcvu095_0
+
 [parameter NUM_CORES]
 datatype = int
 paramtype = vlogparam

diff --git a/examples/fpga/vcu108/system_2x2_cccc/system_2x2_cccc_vcu108.system b/examples/fpga/vcu108/system_2x2_cccc/system_2x2_cccc_vcu108.system