sipeed/m1s-dock: run code on 64-bit core

Signed-off-by: Daniel Maslowski <info@orangecms.org>

src/mainboard/sipeed/m1s-dock/e907/src/init.rs

@@ -4,14 +4,19 @@ const GLB_BASE: usize = 0x2000_0000;
 pub const SWRST_CFG2: usize = GLB_BASE + 0x0548;
 const CPU_RST: u32 = 1 << 1;
 
+pub const MM_BASE: usize = 0x3000_0000;
+
+
 const MM_GLB_BASE: usize = 0x3000_7000;
+const MM_SYS_CTRL: usize = MM_GLB_BASE;
 const MM_SW_SYS_RESET: usize = MM_GLB_BASE + 0x0040;
 const SYS_RESET: u32 = 1 << 0;
 const PWRON_RST: u32 = 1 << 2;
 const MMCPU0_RESET: u32 = 1 << 8;
 const MMCPU1_RESET: u32 = 1 << 9;
 const WL2MM_RST_MSK: u32 = 1 << 15;
 const MM_RESUME: u32 = SYS_RESET | PWRON_RST | MMCPU1_RESET | WL2MM_RST_MSK;
+const MM_CLK_EN: u32 = 1 << 12;
 
 pub fn reset_cpu() {
     unsafe {
@@ -20,8 +25,15 @@ pub fn reset_cpu() {
     }
 }
 
-pub fn resume_mm() {
+// see https://github.com/smaeul/opensbi/commit/487866632bba84871e773c90bf874ab6d81065aa
+pub fn resume_mm(entry: u32) {
     unsafe {
+        /* Flush the data cache */
+        core::arch::asm!(".word 0x0010000b");
+        core::arch::asm!(".word 0x01a0000b");
+        core::ptr::write_volatile(MM_BASE as *mut u32, entry);
+        let e = core::ptr::read_volatile(MM_SYS_CTRL as *mut u32);
+        core::ptr::write_volatile(MM_SYS_CTRL as *mut u32, e | MM_CLK_EN);
         let s = core::ptr::read_volatile(MM_SW_SYS_RESET as *mut u32);
         core::ptr::write_volatile(MM_SW_SYS_RESET as *mut u32, s & MM_RESUME);
     }

src/mainboard/sipeed/m1s-dock/e907/src/main.rs

@@ -118,10 +118,13 @@ fn main() {
         sleep();
     }
 
-    dump(0x3EFF0000, 32);
+    const MM_ENTRY: usize = 0x3eff_0000;
+    dump(MM_ENTRY, 32);
 
-    init::resume_mm();
-    init::reset_cpu();
+    init::resume_mm(MM_ENTRY as u32);
+    if false {
+        init::reset_cpu();
+    }
 }
 
 #[cfg_attr(not(test), panic_handler)]