Make the M cores only poll the state on first construction

oxidecomputer · May 6, 2020 · a485eb4 · a485eb4
1 parent 1da8e45
commit a485eb4
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Showing 3 changed files with 57 additions and 57 deletions.
diff --git a/probe-rs/src/architecture/arm/core/m0.rs b/probe-rs/src/architecture/arm/core/m0.rs
@@ -285,34 +285,34 @@ impl<'probe> M0<'probe> {
         mut memory: Memory<'probe>,
         state: &'probe mut CortexState,
     ) -> Result<Self, Error> {
-        // determine current state
-        let dhcsr = Dhcsr(memory.read_word_32(Dhcsr::ADDRESS)?);
+        if !state.initialized() {
+            // determine current state
+            let dhcsr = Dhcsr(memory.read_word_32(Dhcsr::ADDRESS)?);
 
-        let core_state = if dhcsr.s_sleep() {
-            CoreStatus::Sleeping
-        } else if dhcsr.s_halt() {
-            log::debug!("Core was halted when connecting");
+            let core_state = if dhcsr.s_sleep() {
+                CoreStatus::Sleeping
+            } else if dhcsr.s_halt() {
+                log::debug!("Core was halted when connecting");
 
-            let dfsr = Dfsr(memory.read_word_32(Dfsr::ADDRESS)?);
+                let dfsr = Dfsr(memory.read_word_32(Dfsr::ADDRESS)?);
 
-            let reason = dfsr.halt_reason();
+                let reason = dfsr.halt_reason();
 
-            CoreStatus::Halted(reason)
-        } else {
-            CoreStatus::Running
-        };
+                CoreStatus::Halted(reason)
+            } else {
+                CoreStatus::Running
+            };
+
+            // Clear DFSR register. The bits in the register are sticky,
+            // so we clear them here to ensure that that none are set.
+            let dfsr_clear = Dfsr::clear_all();
+
+            memory.write_word_32(Dfsr::ADDRESS, dfsr_clear.into())?;
 
-        if !state.initialized() {
             state.current_state = core_state;
             state.initialize();
         }
 
-        // Clear DFSR register. The bits in the register are sticky,
-        // so we clear them here to ensure that that none are set.
-        let dfsr_clear = Dfsr::clear_all();
-
-        memory.write_word_32(Dfsr::ADDRESS, dfsr_clear.into())?;
-
         Ok(Self { memory, state })
     }
 

diff --git a/probe-rs/src/architecture/arm/core/m33.rs b/probe-rs/src/architecture/arm/core/m33.rs
@@ -29,34 +29,34 @@ impl<'probe> M33<'probe> {
         mut memory: Memory<'probe>,
         state: &'probe mut CortexState,
     ) -> Result<Self, Error> {
-        // determine current state
-        let dhcsr = Dhcsr(memory.read_word_32(Dhcsr::ADDRESS)?);
+        if !state.initialized() {
+            // determine current state
+            let dhcsr = Dhcsr(memory.read_word_32(Dhcsr::ADDRESS)?);
 
-        let core_state = if dhcsr.s_sleep() {
-            CoreStatus::Sleeping
-        } else if dhcsr.s_halt() {
-            log::debug!("Core was halted when connecting");
+            let core_state = if dhcsr.s_sleep() {
+                CoreStatus::Sleeping
+            } else if dhcsr.s_halt() {
+                log::debug!("Core was halted when connecting");
 
-            let dfsr = Dfsr(memory.read_word_32(Dfsr::ADDRESS)?);
+                let dfsr = Dfsr(memory.read_word_32(Dfsr::ADDRESS)?);
 
-            let reason = dfsr.halt_reason();
+                let reason = dfsr.halt_reason();
 
-            CoreStatus::Halted(reason)
-        } else {
-            CoreStatus::Running
-        };
+                CoreStatus::Halted(reason)
+            } else {
+                CoreStatus::Running
+            };
+
+            // Clear DFSR register. The bits in the register are sticky,
+            // so we clear them here to ensure that that none are set.
+            let dfsr_clear = Dfsr::clear_all();
+
+            memory.write_word_32(Dfsr::ADDRESS, dfsr_clear.into())?;
 
-        if !state.initialized() {
             state.current_state = core_state;
             state.initialize();
         }
 
-        // Clear DFSR register. The bits in the register are sticky,
-        // so we clear them here to ensure that that none are set.
-        let dfsr_clear = Dfsr::clear_all();
-
-        memory.write_word_32(Dfsr::ADDRESS, dfsr_clear.into())?;
-
         Ok(Self { memory, state })
     }
 

diff --git a/probe-rs/src/architecture/arm/core/m4.rs b/probe-rs/src/architecture/arm/core/m4.rs
@@ -338,34 +338,34 @@ impl<'probe> M4<'probe> {
         mut memory: Memory<'probe>,
         state: &'probe mut CortexState,
     ) -> Result<M4<'probe>, Error> {
-        // determine current state
-        let dhcsr = Dhcsr(memory.read_word_32(Dhcsr::ADDRESS)?);
+        if !state.initialized() {
+            // determine current state
+            let dhcsr = Dhcsr(memory.read_word_32(Dhcsr::ADDRESS)?);
 
-        let core_state = if dhcsr.s_sleep() {
-            CoreStatus::Sleeping
-        } else if dhcsr.s_halt() {
-            log::debug!("Core was halted when connecting");
+            let core_state = if dhcsr.s_sleep() {
+                CoreStatus::Sleeping
+            } else if dhcsr.s_halt() {
+                log::debug!("Core was halted when connecting");
 
-            let dfsr = Dfsr(memory.read_word_32(Dfsr::ADDRESS)?);
+                let dfsr = Dfsr(memory.read_word_32(Dfsr::ADDRESS)?);
 
-            let reason = dfsr.halt_reason();
+                let reason = dfsr.halt_reason();
 
-            CoreStatus::Halted(reason)
-        } else {
-            CoreStatus::Running
-        };
+                CoreStatus::Halted(reason)
+            } else {
+                CoreStatus::Running
+            };
+
+            // Clear DFSR register. The bits in the register are sticky,
+            // so we clear them here to ensure that that none are set.
+            let dfsr_clear = Dfsr::clear_all();
+
+            memory.write_word_32(Dfsr::ADDRESS, dfsr_clear.into())?;
 
-        if !state.initialized() {
             state.current_state = core_state;
             state.initialize();
         }
 
-        // Clear DFSR register. The bits in the register are sticky,
-        // so we clear them here to ensure that that none are set.
-        let dfsr_clear = Dfsr::clear_all();
-
-        memory.write_word_32(Dfsr::ADDRESS, dfsr_clear.into())?;
-
         Ok(Self { memory, state })
     }