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PNA Meeting Minutes Sep 13, 2018
- Gordon Brebner - Xilinx
- James Coole - Cisco
- John Marshall - Cisco
- Marjan Radi - Western Digital
- Mihai Budiu - VMware
- Noa Zilberman - Univ. of Cambridge
- Pietro Bressana - Ph.D student USI Lugano in Switzerland, and Western Digital
- Paul Jardetzky - Netronome
- Sridhar Samudrala - Intel
- Stephen Ibanez - Stanford University, Xilinx
- Yuta Tokusashi - Keio University, Japan, and Western Digital
- Andy Fingerhut - Cisco
Gordon presented from a slide deck he had prepared. Below are very brief notes on a few of the slides, not intended to capture all of the discussion.
Slide title: Xilinx Labs "Type 1, 2 and 3 NIC" prototype
The box labeled with C/C++ uses high level synthesis tools to synthesize C/C++ code to FPGA programming. Probably intended to give someone an easier path to an FPGA accelerated implementation without the customer needing to learn Verilog.
Slide title: Use Case 1/4: Basic NIC ingress and egress
Q: Does this involve TCP offload? Gordon: Not this use case, but wait for a later one.
Slide title: Use Case 2/4: Direct egress to ingress bridging
Note the latency actually reduced in this case. Probably due to DPDK inefficiencies at software boundaries, and partly due to the FPGA-accelerated application logic having lower latency.
Biggest downside is the consumption of PCIe bandwidth.
Slide title: Use case 3/4: NIC with integrated acceleration
Gordon: "I sometimes call P4 'shallow packet inspection'" :-)
Slide title: Basic (fixed) NIC functions plus Programmable NIC functions
John: Do you see P4 on the horizon for NICs, or sooner?
Gordon: Microsoft was using off-the-shelf NIC chip next to the FPGA, and could not change the functionality of the off-the-shelf NIC.
One thing Microsoft engineers would like is "more statefulness" in P4 than it currently makes straightforward.
One paper and one slide deck by Microsoft Azure engineering team that were briefly discussed during the meeting were:
"Azure Accelerated Networking: SmartNICs in the Public Cloud" Daniel Firestone, Andrew Putnam, et al (32 authors!), 15th NSDI - USENIX Symposium on Networked Systems Design and Implementation, 2018 https://www.microsoft.com/en-us/research/uploads/prod/2018/03/Azure_SmartNIC_NSDI_2018.pdf
In particular Section 9 "Related Work" has this quote:
"The P4 specification offers flexible parsing and relatively flexible actions, many of which are similar to GFT. In fact, P4 could potentially serve as a way to specify some of the GFT processing flow. However, there are other SDN functions outside the scope of existing P4 engines and even the P4 language specification that are important for us to implement in AccelNet -- functions such as scheduling, QoS, background state updates, any kind of programmable transport layer, and a variety of complex policies outside the scope of simple packet transformations. While we expect the P4 language to be extended to include many of these, using a programmable fabric like an FPGA to implement GFT or P4 functionality remains a good choice given the evolving nature of the SDN and cloud space. We expect much of the functionality outside of the core packet processor to harden over time, but ex- pect SDN to remain soft for the foreseeable future."
"Virtual Filtering Platform: A retrospective on 8 years of shipping Host SDN in the Public Cloud", Daniel Firestone, Tech Lead and Manager, Azure Networking Host SDN Team https://www.usenix.org/sites/default/files/conference/protected-files/nsdi17_slides_firestone.pdf