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De-tabbed source files; merged all AHDL/Verilog to one directory #1

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@jacgoudsmit jacgoudsmit commented Jan 14, 2015

For those reading along: Please note!

This pull request is now so stale that I decided to abandon the Master branch. The Rel branch of my P1V repository is where the latest version of the P1V sources live. The Rel branch has some important bug fixes that are not in the Parallax repository!

See https://github.com/jacgoudsmit/P1V

Original pull request follows:

After I forked the repo from Parallaxinc, I started by detabbing each and every file using Notepad++. The Spin files used 8-space tabs, the Verilog/AHDL files used 4-space tabs.

Then I added .gitignore to make sure that temporary files and output files won't get added in the future. That means that the .jic files that were previously in the repository will be excluded too; that's okay because those aren't needed by developers and just waste bandwidth when cloning the repository to a local drive. We can just make them into downloadable files.

The biggest part of this change was moving all source files into one directory called HDL. This way, we don't have duplicate files in the repository, and it won't be necessary to perform the same bug fixes in multiple directories. In other words, whenever someone makes a change to (say) the DE0-Nano repository, it won't be necessary to copy or integrate those changes into the other directories.

I modified the code in HDL so that it's possible to disable the character ROM in the DE0-Nano, and invert the LEDs on the BeMicroCV. I renamed the original top.qsf files to names that represent each of the Altera targets, and added all Altera targets as "revisions" of a new P1V_Altera.qpf project file. This makes it possible to maintain and build all Altera targets without closing the project in Quartus II.

The result is mostly identical to the master branch of the old P8X32A_Emulation repository by Heater, Mindrobots, me, and others but I avoided some mistakes we made before.

Thanks for reading!

jacgoudsmit and others added 9 commits January 10, 2015 22:08
- Copied all source files to the HDL directory
- Renamed the project file from top.qpf to P1V_Altera.qpf
- Renamed and added the various top.qsf files
- Removed the files from the old locations
- Change the configuration to use an output_files directory for reduced clutter
- Added a definition to the DE0-Nano project and an `ifdef/`endif to hub_mem.v to remove the character ROM for that target only
- Added a parameter override to the BeMicroCV project and modified dig.v to use it to invert the cog LEDs for that target only
- Modified the readme.txt files in all directories (TODO: update the PDF files)
- Moved the gpl.txt file to the root of the project
[Seairth] Added SDC files for DE0-Nano and DE2-115
The PLL simulator was written when Parallax released the Verilog sources, but a tiny bug snuck in: some configuration bits should be NORed instead of NANDed.
Forum discussion: see http://forums.parallax.com/discussion/157387
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