Description

Compare finite state machine (FSM) coding styles in Bluespec SystemVerilog (BSV) in comparition to SystemVerilog.

Quickstart

Create an environment for BSC

source env.sh

Bluespec simulation

bsc -sim -u ./test/Tb1.bsv
bsc -sim -e mkTb
./bsim -V

Create RTL

bsc -verilog -u ./test/Tb1.bsv

Lint

verilator -Wall --lint-only -f verilator.f ./test/top.sv

SystemVerilog simulation

verilator -Wall -f verilator.f --cc --exe --build ./test/top.sv sim_main.cpp
./obj_dir/Vtop

References

• Clifford E. Cummings, Heath Chambers, "Finite State Machine (FSM) Design & Synthesis using SystemVerilog - Part I"