GitHub - pbzweihander/Microprocessor: Microprocessor implemented with Verilog, for Logic Design Lab Final Project.

pbzweihander / Microprocessor Public

Microprocessor implemented with Verilog, for Logic Design Lab Final Project.

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Name		Name	Last commit message	Last commit date
Latest commit History 12 Commits
ALU.v		ALU.v
ClockDivider.v		ClockDivider.v
Control.v		Control.v
ControlTest.v		ControlTest.v
DataMemory.v		DataMemory.v
DataMemoryTest.v		DataMemoryTest.v
HexDecoder.v		HexDecoder.v
IntegrationTest.v		IntegrationTest.v
Microprocessor.v		Microprocessor.v
MicroprocessorWithTestInst.v		MicroprocessorWithTestInst.v
OpDecoder.v		OpDecoder.v
Registers.v		Registers.v
RegistersTest.v		RegistersTest.v
TestProcessorTest.v		TestProcessorTest.v