A five-stage RISC-V pipeline processor written in Verilog
Course: Computer Organization by T.F. Chen (NYCU 2021 Spring)
Team of 2: JY Lin, SW Li
- Five stages: IF, ID, EX, MEM and WB
- Implements every component in a CPU except program counter, instruction memory, and registers
- Supports Forwarding, Flush, and Hazard Detection