Merge 9ef1239 into 93a69ff

magma/fromverilog.py

@@ -17,6 +17,7 @@
 from .passes.tsort import tsort
 
 import logging
+from hwtypes import UIntVector, SIntVector
 
 logger = logging.getLogger('magma').getChild('from_verilog')
 
@@ -87,9 +88,51 @@ def convert(input_type, target_type):
     raise NotImplementedError(f"Conversion between {input_type} and "
                               f"{target_type} not supported")
 
+
+def parse_int_const(value):
+    if "'" in value:
+        # Parse literal specifier
+        size, value = value.split("'")
+        if size == "":
+            size = 32
+        else:
+            size = int(size)
+        if "s" in value:
+            signed = True
+            value = value.replace("s", "")
+        else:
+            signed = False
+        if "h" in value:
+            value = value.replace("h", "")
+            base = 16
+        elif "o" in value:
+            value = value.replace("o", "")
+            base = 8
+        elif "b" in value:
+            value = value.replace("b", "")
+            base = 2
+        elif "d" in value:
+            value = value.replace("d", "")
+            base = 10
+        else:
+            # default base 10
+            base = 10
+    else:
+        # Default no specifier
+        size = 32
+        base = 10
+        signed = False
+    value = int(value, base)
+    if signed:
+        value = SIntVector[size](value).as_uint()
+    else:
+        value = UIntVector[size](value).as_uint()
+    return value
+
+
 def get_value(v, param_map):
     if isinstance(v, pyverilog_ast.IntConst):
-        return int(v.value)
+        return parse_int_const(v.value)
     if isinstance(v, pyverilog_ast.Rvalue):
         return get_value(v.var, param_map)
     if isinstance(v, (pyverilog_ast.Minus, pyverilog_ast.Uminus)):

tests/test_verilog/gold/test_int_literal_inst.v

@@ -0,0 +1,10 @@
+    module mod #(parameter KRATOS_INSTANCE_ID = 32'h0)
+    (
+        input I
+    );
+
+    endmodule   // mod
+module Top (input I);
+mod mod_inst0(.I(I));
+endmodule
+

tests/test_verilog/gold/test_int_literal_top.v

@@ -0,0 +1,6 @@
+    module mod #(parameter KRATOS_INSTANCE_ID = 32'h0)
+    (
+        input I
+    );
+
+    endmodule   // mod

tests/test_verilog/test_from_file.py

@@ -233,3 +233,30 @@ def test_nd_array_decl():
       input [7:0] inp [3:0][1:0];
     endmodule"""
     _test_nd_array_port(verilog)
+
+def test_int_literal():
+    verilog = """
+    module mod #(parameter KRATOS_INSTANCE_ID = 32'h0)
+    (
+        input I
+    );
+
+    endmodule   // mod
+    """
+
+    [mod] = m.DefineFromVerilog(verilog)
+    m.compile("build/test_int_literal_top", mod, output="verilog")
+    assert m.testing.check_files_equal(
+        __file__, "build/test_int_literal_top.v",
+        "gold/test_int_literal_top.v")
+
+    class Top(m.Circuit):
+        IO = ["I", m.In(m.Bit)]
+        @classmethod
+        def definition(io):
+            mod()(io.I)
+
+    m.compile("build/test_int_literal_inst", Top)
+    assert m.testing.check_files_equal(
+        __file__, "build/test_int_literal_inst.v",
+        "gold/test_int_literal_inst.v")