Merge 4c771d2 into 7bd2264

magma/backend/coreir_.py

@@ -134,13 +134,15 @@ def to_string(k):
                 _type = self.context.named_types[("coreir", "arst")]
             else:
                 _type = self.context.Bit()
-        else:
+        elif port.isoutput():
             if isinstance(port, (ClockType, ClockKind)):
                 _type = self.context.named_types[("coreir", "clkIn")]
             elif isinstance(port, (AsyncResetType, AsyncResetKind)):
                 _type = self.context.named_types[("coreir", "arstIn")]
             else:
                 _type = self.context.BitIn()
+        else:
+            _type = self.context.BitInOut()
         return _type
 
     coreirNamedTypeToPortDict = {
@@ -274,21 +276,23 @@ def compile_definition_to_module_definition(self, definition, module_definition)
 
         for instance in definition.instances:
             for name, port in instance.interface.ports.items():
-                self.connect_input(module_definition, port, non_input_ports)
+                self.connect_non_outputs(module_definition, port,
+                                         non_input_ports)
 
         for port in definition.interface.ports.values():
-            self.connect_input(module_definition, port,
-                               non_input_ports)
+            self.connect_non_outputs(module_definition, port, non_input_ports)
 
-    def connect_input(self, module_definition, port,
+    def connect_non_outputs(self, module_definition, port,
                       non_input_ports):
-        if not port.isinput():
-            if isinstance(port, (TupleType, ArrayType)):
-                for elem in port:
-                    self.connect_input(module_definition, elem,
-                                       non_input_ports)
-            return
-        self.connect(module_definition, port, port.value(), non_input_ports)
+        # Recurse into non input types that may contain inout children
+        if isinstance(port, TupleType) and not port.isinput() or \
+                isinstance(port, ArrayType) and not port.T.isinput():
+            for elem in port:
+                self.connect_non_outputs(module_definition, elem,
+                                         non_input_ports)
+        elif not port.isoutput():
+            self.connect(module_definition, port, port.value(),
+                         non_input_ports)
 
     def compile_definition(self, definition):
         logger.debug(f"Compiling definition {definition}")
@@ -333,6 +337,9 @@ def is_clock_or_nested_clock(p):
         if value is None and is_clock_or_nested_clock(port):
             return
         elif value is None:
+            if port.isinout():
+                # Skip inouts because they might be connected as an input
+                return
             raise Exception(f"Got None for port '{port.debug_name}', is it "
                             "connected to anything?")
         elif isinstance(value, coreir.Wireable):

tests/test_verilog/gold/test_pad.v

@@ -14,7 +14,7 @@ module PRWDWUWSWCDGH_V (
   input  I,
   input  IE,
   input  OEN,
-  output  PAD,
+  inout  PAD,
   input  PD,
   input  PU,
   input  RTE,
@@ -26,7 +26,7 @@ endmodule  // PRWDWUWSWCDGH_V
 
 */
 module Top (
-  output  pad
+  inout  pad
 );
 
 
@@ -76,7 +76,7 @@ module Top (
 
   assign PRWDWUWSWCDGH_V_inst0__OEN = bit_const_0_None__out;
 
-  assign pad = PRWDWUWSWCDGH_V_inst0__PAD;
+  assign PRWDWUWSWCDGH_V_inst0__PAD = pad;
 
   assign PRWDWUWSWCDGH_V_inst0__PD = bit_const_0_None__out;
 

tests/test_verilog/test_from_file.py

@@ -94,12 +94,12 @@ def test_from_sv():
                                        "test_pe.sv")
 
 
-def test_from_pad():
+def test_from_pad_inout():
     file_path = os.path.dirname(__file__)
     Pad = m.DeclareFromVerilogFile(os.path.join(file_path, "pad.v"))[0]
 
     class Top(m.Circuit):
-        IO = ["pad", m.Out(m.Bit)]
+        IO = ["pad", m.InOut(m.Bit)]
         @classmethod
         def definition(io):
             pad = Pad()