Merge pull request #462 from phanrahan/magma-fix-parser

Parse n-d array types in verilog ports

.travis.yml

@@ -30,7 +30,8 @@ install:
 
 - pip install twine
 - pip install python-coveralls
-- pip install pytest-cov pytest-codestyle
+- pip install pytest-cov pytest-codestyle fault
+- pip install --ignore-installed -r requirements.txt
 - pip install -e .
 after_success:
 - coveralls

README.md

@@ -117,6 +117,7 @@ $ cd magma
 
 Install magma as a symbolic package
 ```
+$ pip install -r requirements.txt
 $ pip install -e .
 ```
 

magma/fromverilog.py

@@ -11,6 +11,7 @@
 from .t import In, Out, InOut
 from .bit import Bit, _BitKind
 from .bits import Bits, BitsKind
+from .array import Array
 from .circuit import DeclareCircuit, DefineCircuit, EndDefine
 
 from .passes.tsort import tsort
@@ -100,6 +101,13 @@ def get_value(v, param_map):
     else:
         raise NotImplementedError(type(v))
 
+
+def get_width(width, param_map):
+    msb = get_value(width.msb, param_map)
+    lsb = get_value(width.lsb, param_map)
+    return msb - lsb + 1
+
+
 def get_type(io, type_map, param_map):
     if isinstance(io, Input):
         direction = In
@@ -109,18 +117,24 @@ def get_type(io, type_map, param_map):
         direction = InOut
 
     if io.width is None:
-        type_ = Bit
+        typ = Bit
     else:
-        msb = get_value(io.width.msb, param_map)
-        lsb = get_value(io.width.lsb, param_map)
-        type_ = Bits[msb-lsb+1]
+        width = get_width(io.width, param_map)
+        typ = Bits[width]
+
+    # Generate multidimensional arrays if necessary. Note that we guard with
+    # hasattr to make this backwards compatible.
+    if hasattr(io, "dimensions") and io.dimensions is not None:
+        for length in reversed(io.dimensions.lengths):
+            width = get_width(length, param_map)
+            typ = Array[width, typ]
 
-    type_ = direction(type_)
+    typ = direction(typ)
 
     if io.name in type_map:
-        type_ = convert(type_, type_map[io.name])
+        typ = convert(typ, type_map[io.name])
 
-    return type_
+    return typ
 
 
 def ParseVerilogModule(node, type_map):

requirements.txt

@@ -0,0 +1 @@
+-e git+git://github.com/leonardt/Pyverilog.git@add-nd-arrays#egg=pyverilog

setup.py

@@ -28,7 +28,7 @@
         "astor",
         "six",
         "mako",
-        "pyverilog",
+        # "pyverilog",
         "numpy",
         "graphviz",
         "coreir>=2.0.*",

tests/test_verilog/test_from_file.py

@@ -204,3 +204,28 @@ def test_from_verilog_external_modules_duplicate():
     assert pytest_e.type is Exception
     assert pytest_e.value.args == \
         ("Modules defined in both external_modules and in parsed verilog: {'foo'}",)  # nopep8
+
+
+def _test_nd_array_port(verilog):
+    [top] = m.DefineFromVerilog(verilog)
+    assert len(top.interface.ports) == 1
+    assert "inp" in top.interface.ports
+
+    # Not sure why the following doesn't work, using repr as a workaround.
+    #assert type(top.inp) is m.In(m.Array[4, m.Array[2, m.Bits[8]]])
+    assert repr(type(top.inp)) == "Array[4, Array[2, Bits[8, Bit]]]"
+
+
+def test_nd_array_port_list():
+    verilog = """
+    module top (input [7:0] inp [3:0][1:0]);
+    endmodule"""
+    _test_nd_array_port(verilog)
+
+
+def test_nd_array_decl():
+    verilog = """
+    module top (inp);
+      input [7:0] inp [3:0][1:0];
+    endmodule"""
+    _test_nd_array_port(verilog)