Simplify logic since we're not using the type to rename

phanrahan · May 9, 2019 · 63a1b35 · 63a1b35
1 parent ad28e3d
commit 63a1b35
Showing 1 changed file with 4 additions and 7 deletions.
diff --git a/magma/backend/coreir_.py b/magma/backend/coreir_.py
@@ -160,15 +160,12 @@ def get_ports(self, coreir_type, renamed_ports):
         elif (coreir_type.kind == "Record"):
             elements = {}
             for item in coreir_type.items():
+                name = item[0]
                 # replace  the in port with I as can't reference that
-                name = "I" if (item[0] == "in") else item[0]
-                elements[name] = self.get_ports(item[1], renamed_ports)
-                # save the renaming data for later use
-                if item[0] == "in":
-                    if isinstance(elements[name], BitKind):
-                        # making a copy of bit, as don't want to affect all other bits
-                        elements[name] = MakeBit(direction=elements[name].direction)
+                if name == "in":
+                    name = "I"
                     renamed_ports[name] = "in"
+                elements[name] = self.get_ports(item[1], renamed_ports)
             return Tuple(**elements)
         elif (coreir_type.kind == "Named"):
             # exception to handle clock types, since other named types not handled