Add signed test

phanrahan · Dec 11, 2019 · f215f06 · f215f06
1 parent 6bdb418
commit f215f06
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Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/tests/test_verilog/gold/test_int_literal_inst.v b/tests/test_verilog/gold/test_int_literal_inst.v
@@ -16,7 +16,7 @@ module mod3 #(parameter KRATOS_INSTANCE_ID = 16'b1)
 );
 
 endmodule   // mod
-module mod2 #(parameter KRATOS_INSTANCE_ID = 24'd2)
+module mod2 #(parameter KRATOS_INSTANCE_ID = 24'sd2)
 (
     input I
 );

diff --git a/tests/test_verilog/gold/test_int_literal_mod2.v b/tests/test_verilog/gold/test_int_literal_mod2.v
@@ -1,4 +1,4 @@
-module mod2 #(parameter KRATOS_INSTANCE_ID = 24'd2)
+module mod2 #(parameter KRATOS_INSTANCE_ID = 24'sd2)
 (
     input I
 );

diff --git a/tests/test_verilog/test_from_file.py b/tests/test_verilog/test_from_file.py
@@ -236,7 +236,7 @@ def test_nd_array_decl():
 
 
 def test_int_literal():
-    literals = ["32'h0", "'h1", "24'd2", "16'b1", "13'o7", "17"]
+    literals = ["32'h0", "'h1", "24'sd2", "16'b1", "13'o7", "17"]
     verilog = ""
     for i, literal in enumerate(literals):
         verilog += f"""