Registers

Registers

As Skiron is a RISC-inspired architecture, a high register count is one of its design goals. To wit, it has 64 general registers, with 1 extended (not directly accessible) register(s). However, the upper 5 registers are reserved for use with specific instructions and/or CPU operation; while they can be accessed, they are not guaranteed to operate the same way as regular registers.

Standard Registers

The standard registers have specific behaviours associated with them. These behaviours can be found in the description for each register.

• z
  • Index: 59
  • Description: Zero register (always 0). Any writes to this register will be discarded; any reads will always return 0.
• ra
  • Index: 60
  • Description: Return address (address to return to after the current function executes). To automatically save and restore the return address on the stack, use the callsv instruction.
• bp
  • Index: 61
  • Description: The stack base pointer (address of the start of this function's stack).
• sp
  • Index: 62
  • Description: The stack pointer (address of the element on the top of the stack). This is typically modified by pseudo-instructions like push, pop, and callsv.
• ip
  • Index: 63
  • Description: The instruction pointer (address of the instruction being executed). This is modified by normal CPU operation, as well as jump/call instructions. This register can be the target of move instructions; the jr pseudoinstruction is a move instruction.

Extended Registers

The extended registers are not directly accessible through normal means. They are typically used for information exclusive to the CPU, such as the value of the last conditional comparison (cmp) undertaken.

• flags
  • Index: 64
  • Description: A bitmask of flags set by the CPU during operation. Typically used for conditional branching instructions.
  • Values:
    • None: 0
    • Zero: 1 << 0
    • Greater: 1 << 1
    • Less: 1 << 2