Optimize access to thread local cache.

This patch saves one CPU instruction on each "_tsrm_ls_cache" access in ZTS CLI/CGI/FPM builds. This reduce typical instruction sequence for EG(current_execute_data) access from 4 to 3 CPU instructions.
php · Sep 18, 2019 · 2aefd11 · cmb69 · Sep 20, 2019 · dstogov
1 parent d7b4cdf
commit 2aefd11
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Showing 2 changed files with 18 additions and 2 deletions.
diff --git a/TSRM/TSRM.h b/TSRM/TSRM.h
@@ -143,6 +143,14 @@ TSRM_API const char *tsrm_api_name(void);
 # define TSRM_TLS __thread
 #endif
 
+#if !defined(__has_attribute) || !__has_attribute(tls_model)
+# define TSRM_TLS_MODEL_ATTR
+#elif __PIC__
+# define TSRM_TLS_MODEL_ATTR __attribute__((tls_model("initial-exec")))
+#else
+# define TSRM_TLS_MODEL_ATTR __attribute__((tls_model("local-exec")))
+#endif
+
 #define TSRM_SHUFFLE_RSRC_ID(rsrc_id)		((rsrc_id)+1)
 #define TSRM_UNSHUFFLE_RSRC_ID(rsrc_id)		((rsrc_id)-1)
 
@@ -155,8 +163,8 @@ TSRM_API const char *tsrm_api_name(void);
 #define TSRMG_BULK_STATIC(id, type)	((type) (*((void ***) TSRMLS_CACHE))[TSRM_UNSHUFFLE_RSRC_ID(id)])
 #define TSRMG_FAST_STATIC(offset, type, element)	(TSRMG_FAST_BULK_STATIC(offset, type)->element)
 #define TSRMG_FAST_BULK_STATIC(offset, type)	((type) (((char*) TSRMLS_CACHE)+(offset)))
-#define TSRMLS_CACHE_EXTERN() extern TSRM_TLS void *TSRMLS_CACHE;
-#define TSRMLS_CACHE_DEFINE() TSRM_TLS void *TSRMLS_CACHE = NULL;
+#define TSRMLS_CACHE_EXTERN() extern TSRM_TLS void *TSRMLS_CACHE TSRM_TLS_MODEL_ATTR;
+#define TSRMLS_CACHE_DEFINE() TSRM_TLS void *TSRMLS_CACHE TSRM_TLS_MODEL_ATTR = NULL;
 #define TSRMLS_CACHE_UPDATE() TSRMLS_CACHE = tsrm_get_ls_cache()
 #define TSRMLS_CACHE _tsrm_ls_cache
 

diff --git a/ext/opcache/jit/zend_jit_x86.dasc b/ext/opcache/jit/zend_jit_x86.dasc
@@ -2366,13 +2366,21 @@ static int zend_jit_setup(void)
 # elif defined(__GNUC__) && defined(__x86_64__)
 	tsrm_ls_cache_tcb_offset = tsrm_get_ls_cache_tcb_offset();
 	if (tsrm_ls_cache_tcb_offset == 0) {
+#if defined(__has_attribute) && __has_attribute(tls_model)
+		size_t ret;
+
+		asm ("movq _tsrm_ls_cache@gottpoff(%%rip),%0"
+			: "=r" (ret));
+		tsrm_ls_cache_tcb_offset = ret;
+#else
 		size_t *ti;
 
 		__asm__(
 			"leaq _tsrm_ls_cache@tlsgd(%%rip), %0\n"
 			: "=a" (ti));
 		tsrm_tls_offset = ti[1];
 		tsrm_tls_index = ti[0] * 16;
+#endif
 	}
 # elif defined(__GNUC__) && defined(__i386__)
 	tsrm_ls_cache_tcb_offset = tsrm_get_ls_cache_tcb_offset();