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RISC-V: Add TARGET_MIN_VLEN > 4096 check
gcc/ChangeLog: * config/riscv/riscv.cc (riscv_option_override): Add sorry check. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/zvl-unimplemented-1.c: New test. * gcc.target/riscv/rvv/base/zvl-unimplemented-2.c: New test.
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gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-1.c
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Original file line number | Diff line number | Diff line change |
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/* { dg-do compile } */ | ||
/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=fixed-vlmax" } */ | ||
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void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" } |
4 changes: 4 additions & 0 deletions
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gcc/testsuite/gcc.target/riscv/rvv/base/zvl-unimplemented-2.c
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,4 @@ | ||
/* { dg-do compile } */ | ||
/* { dg-options "-O3 -march=rv64gcv_zvl8192b -mabi=lp64d --param riscv-autovec-preference=scalable" } */ | ||
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void foo () {} // { dg-excess-errors "sorry, unimplemented: Current RISC-V GCC can not support VLEN > 4096bit for 'V' Extension" } |