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Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

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Computer-Organisation

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003 (Computer Organisation) during fall semester of 2019.

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Final codes for each part is commented denoting the use of particular code block and each part contains a README.md file explaining the problem statement and the approach to solve it.

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Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003, Introduction to Computer Organisation in IIT Madras.

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