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This repository has been archived by the owner on Dec 13, 2022. It is now read-only.
The SystemVerilog layer should not have any Cava kernel specific features in it i.e. it should be a fairly direct and neutral representation of the subset of SystemVerilog that we generate.
The text was updated successfully, but these errors were encountered:
This allows us to have modules written in different languages.
For now, we just move this to a subfolder, a future commit will add the
cpp version. Everything should work as before for now.
The SystemVerilog layer should not have any Cava kernel specific features in it i.e. it should be a fairly direct and neutral representation of the subset of SystemVerilog that we generate.
The text was updated successfully, but these errors were encountered: