Skip to content
This repository has been archived by the owner on Dec 13, 2022. It is now read-only.

Add a SystemVerilog layer below the Netlist layer #142

Closed
satnam6502 opened this issue Jun 9, 2020 · 2 comments
Closed

Add a SystemVerilog layer below the Netlist layer #142

satnam6502 opened this issue Jun 9, 2020 · 2 comments
Assignees
@satnam6502
Labels
P2

Comments

@satnam6502
Copy link
Contributor

The SystemVerilog layer should not have any Cava kernel specific features in it i.e. it should be a fairly direct and neutral representation of the subset of SystemVerilog that we generate.
@satnam6502 satnam6502 self-assigned this Jun 9, 2020
@satnam6502 satnam6502 added the P1 label Jun 9, 2020
jadephilipoom pushed a commit to jadephilipoom/oak-hardware that referenced this issue Sep 22, 2020
Move rust examples to a different folder (project-oak#142)
848fc3d 
This allows us to have modules written in different languages.
For now, we just move this to a subfolder, a future commit will add the
cpp version. Everything should work as before for now.
@jadephilipoom jadephilipoom mentioned this issue Oct 7, 2020
Closed
@satnam6502 satnam6502 added P2 and removed P1 labels Oct 8, 2020
@satnam6502
Copy link
Contributor Author

I am reducing the priority on this to P2 because there are other many more important things to do.

@satnam6502
Copy link
Contributor Author

Deprecate.

Sign up for free to subscribe to this conversation on GitHub. Already have an account? Sign in.
Assignees

@satnam6502 satnam6502

Labels
P2
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
1 participant
@satnam6502