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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,41 @@ | ||
Add RISC-V detection | ||
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Upstream commit: | ||
- Qt 5.14: 9a6a84731131b205f74b10f866ae212e0895bd4a | ||
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--- old/qtbase/src/corelib/global/archdetect.cpp | ||
+++ new/qtbase/src/corelib/global/archdetect.cpp | ||
@@ -67,6 +67,10 @@ | ||
# define ARCH_PROCESSOR "power" | ||
#elif defined(Q_PROCESSOR_POWER_64) | ||
# define ARCH_PROCESSOR "power64" | ||
+#elif defined(Q_PROCESSOR_RISCV_32) | ||
+# define ARCH_PROCESSOR "riscv32" | ||
+#elif defined(Q_PROCESSOR_RISCV_64) | ||
+# define ARCH_PROCESSOR "riscv64" | ||
#elif defined(Q_PROCESSOR_S390_X) | ||
# define ARCH_PROCESSOR "s390x" | ||
#elif defined(Q_PROCESSOR_S390) | ||
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--- old/qtbase/src/corelib/global/qprocessordetection.h | ||
+++ old/qtbase/src/corelib/global/qprocessordetection.h | ||
@@ -282,6 +282,19 @@ | ||
// Q_BYTE_ORDER not defined, use endianness auto-detection | ||
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+ /* | ||
+ RISC-V family, known variants: 32- and 64-bit | ||
+ RISC-V is little-endian. | ||
+*/ | ||
+#elif defined(__riscv) | ||
+# define Q_PROCESSOR_RISCV | ||
+# if __riscv_xlen == 64 | ||
+# define Q_PROCESSOR_RISCV_64 | ||
+# else | ||
+# define Q_PROCESSOR_RISCV_32 | ||
+# endif | ||
+# define Q_BYTE_ORDER Q_LITTLE_ENDIAN | ||
+ | ||
/* | ||
S390 family, known variant: S390X (64-bit) | ||
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S390 is big-endian. |