Added 65 8D opcode ([ARM64_DYNAREC] too) (for #766)

ptitSeb · May 5, 2023 · cf22cbc · cf22cbc
1 parent e444b27
commit cf22cbc
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diff --git a/src/dynarec/arm64/dynarec_arm64_64.c b/src/dynarec/arm64/dynarec_arm64_64.c
@@ -570,6 +570,23 @@ uintptr_t dynarec64_64(dynarec_arm_t* dyn, uintptr_t addr, uintptr_t ip, int nin
             }
             break;
 
+        case 0x8D:
+            INST_NAME("LEA Gd, Ed");
+            nextop=F8;
+            GETGD;
+            if(MODREG) {   // reg <= reg? that's an invalid operation
+                DEFAULT;
+            } else {                    // mem <= reg
+                addr = geted(dyn, addr, ninst, nextop, &ed, gd, &fixedaddress, NULL, 0, 0, rex, NULL, 0, 0);
+                if(gd!=ed) {    // it's sometimes used as a 3 bytes NOP
+                    MOVxw_REG(gd, ed);
+                }
+                else if(!rex.w) {
+                    MOVw_REG(gd, gd);   //truncate the higher 32bits as asked
+                }
+            }
+            break;
+
         case 0xC6:
             INST_NAME("MOV Seg:Eb, Ib");
             grab_segdata(dyn, addr, ninst, x4, seg);

diff --git a/src/emu/x64run64.c b/src/emu/x64run64.c
@@ -401,6 +401,16 @@ uintptr_t Run64(x64emu_t *emu, rex_t rex, int seg, uintptr_t addr)
                 GD->q[0] = ED->dword[0];
             break;
 
+        case 0x8D:                      /* LEA Gd,M */
+            nextop = F8;
+            GETGD;
+            tmp64u = GETEA(0);
+            if(rex.w)
+                GD->q[0] = tmp64u;
+            else
+                GD->q[0] = tmp64u&0xffffffff;
+            break;
+
         case 0xA1:                      /* MOV EAX,FS:Od */
             tmp64u = F64;
             if(rex.w)