cleanup
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (6)
hw/cheshire_soc.sv|32 col 34| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1369 col 50| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1379 col 15| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1388 col 44| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1394 col 44| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1399 col 101| Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 32 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L32
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:32 column:34}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:32 column:34} end:{line:33}} text:" input logic eth_clk_90,\n"}
Check warning on line 1369 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1369
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1369 column:50}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1369 column:50} end:{line:1370}} text:" .DataWidth ( Cfg.AxiDataWidth ),\n"}
Check warning on line 1379 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1379
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1379 column:15}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1379 column:15} end:{line:1380}} text:" .rst_ni,\n"}
Check warning on line 1388 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1388
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1388 column:44}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1388 column:44} end:{line:1389}} text:" .phy_resetn_o ( eth_rstn_o ),\n"}
Check warning on line 1394 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1394
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1394 column:44}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1394 column:44} end:{line:1395}} text:" .phy_mdc_o ( eth_mdc_o ),\n"}
Check warning on line 1399 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1399
Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 129 [Style: line-length] [line-length]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1399 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}