add hardcoded dma contrl signals #2399
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (6)
hw/bootrom/cheshire_bootrom.sv|2084 col 10| File must end with a newline. [Style: posix-file-endings] [posix-eof]
hw/cheshire_soc.sv|1305 col 50| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1321 col 15| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1331 col 45| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/cheshire_soc.sv|1337 col 45| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/dma_core_wrap.sv|357 col 10| File must end with a newline. [Style: posix-file-endings] [posix-eof]
Filtered Findings (0)
Annotations
Check warning on line 2084 in hw/bootrom/cheshire_bootrom.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/bootrom/cheshire_bootrom.sv#L2084
File must end with a newline. [Style: posix-file-endings] [posix-eof]
Raw output
message:"File must end with a newline. [Style: posix-file-endings] [posix-eof]" location:{path:"hw/bootrom/cheshire_bootrom.sv" range:{start:{line:2084 column:10}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:2084 column:10} end:{line:2085}} text:"endmodule\n"}
Check warning on line 1305 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1305
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1305 column:50}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1305 column:50} end:{line:1306}} text:" .DataWidth ( Cfg.AxiDataWidth ),\n"}
Check warning on line 1321 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1321
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1321 column:15}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1321 column:15} end:{line:1322}} text:" .rst_ni,\n"}
Check warning on line 1331 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1331
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1331 column:45}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1331 column:45} end:{line:1332}} text:" .phy_resetn_o ( eth_rstn_o ),\n"}
Check warning on line 1337 in hw/cheshire_soc.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_soc.sv#L1337
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/cheshire_soc.sv" range:{start:{line:1337 column:45}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:1337 column:45} end:{line:1338}} text:" .phy_mdc_o ( eth_mdc_o ),\n"}
Check warning on line 357 in hw/dma_core_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/dma_core_wrap.sv#L357
File must end with a newline. [Style: posix-file-endings] [posix-eof]
Raw output
message:"File must end with a newline. [Style: posix-file-endings] [posix-eof]" location:{path:"hw/dma_core_wrap.sv" range:{start:{line:357 column:10}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:357 column:10} end:{line:358}} text:"endmodule\n"}