ci: Extend Github CI and fix first python lint issues

pulp-platform · Aug 18, 2023 · c750c2d · c750c2d
1 parent 7a23533
commit c750c2d
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diff --git a/.github/workflows/build-docker.yml b/.github/workflows/build-docker.yml
@@ -1,4 +1,4 @@
-# Copyright 2020 ETH Zurich and University of Bologna.
+# Copyright 2023 ETH Zurich and University of Bologna.
 # Licensed under the Apache License, Version 2.0, see LICENSE for details.
 # SPDX-License-Identifier: Apache-2.0
 

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -0,0 +1,42 @@
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Run functional regression checks
+name: ci
+on: [push, pull_request]
+jobs:
+
+  #######################
+  # Build SW for Occamy #
+  #######################
+
+  occamy-sw:
+    name: Build SW for Occamy
+    runs-on: ubuntu-22.04
+    container:
+      image: ghcr.io/pulp-platform/occamy
+    steps:
+      - uses: actions/checkout@v2
+        with:
+          submodules: 'recursive'
+      - name: Build Software
+        run: |
+          make -C target/sim sw
+
+  ###############################
+  # Generate Occamy RTL sources #
+  ###############################
+
+  occamy-rtl:
+    name: Generate Occamy RTL sources
+    runs-on: ubuntu-22.04
+    container:
+      image: ghcr.io/pulp-platform/occamy
+    steps:
+      - uses: actions/checkout@v2
+        with:
+          submodules: 'recursive'
+      - name: Generate single-cluster Occamy RTL sources
+        run: |
+          make -C target/sim CFG_OVERRIDE=cfg/single-cluster.hjson rtl
diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml
@@ -0,0 +1,119 @@
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Run all lint checks
+name: lint
+on: [push, pull_request]
+
+jobs:
+
+  ################
+  # Verible Lint #
+  ################
+  verible-lint:
+    name: Lint Verilog sources
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      - uses: chipsalliance/verible-linter-action@main
+        with:
+          paths: |
+            ./hw
+          exclude_paths: |
+            .hw/vendor
+          github_token: ${{ secrets.GITHUB_TOKEN }}
+          fail_on_error: true
+          reviewdog_reporter: github-check
+          extra_args: "--waiver_files util/lint/waiver.verible"
+          verible_version: "v0.0-3318-g8d254167"
+
+  #####################
+  # Vendor Up-to-Date #
+  #####################
+  bender-vendor-up-to-date:
+    name: Check bender vendor up-to-date
+    runs-on: ubuntu-latest
+    steps:
+      - name: Check bender vendor up-to-date
+        uses: pulp-platform/pulp-actions/bender-vendor-up-to-date@v2.1.0
+
+  #################
+  # Check License #
+  #################
+  license-lint:
+    name: Check License headers
+    runs-on: ubuntu-latest
+    steps:
+      - name: Check License
+        uses: pulp-platform/pulp-actions/lint-license@v2.1.0
+        with:
+          patches: 0001-Allow-hash-comments-in-assembly.patch
+          # We cover ETH Zurich and lowRISC licenses and Apache 2.0
+          # (mostly for SW) and Solderpad for the hardware.
+          # yamllint disable rule:line-length
+          license: |
+            Copyright (\d{4}(-\d{4})?\s)?(ETH Zurich and University of Bologna|lowRISC contributors).
+            (Solderpad Hardware License, Version 0.51|Licensed under the Apache License, Version 2.0), see LICENSE for details.
+            SPDX-License-Identifier: (SHL-0.51|Apache-2.0)
+          # yamllint enable rule:line-length
+          match_regex: true
+          exclude_paths: |
+            hw/vendor/
+            util/solder/solder.*.tpl
+
+  ##################
+  # Lint YML Files #
+  ##################
+  yaml-lint:
+    name: Lint YAML Sources
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      - name: yaml-lint
+        uses: ibiqlik/action-yamllint@v3
+        with:
+          config_file: util/lint/.yamllint.yml
+
+  ########################
+  # Check Python Sources #
+  ########################
+  python-lint:
+    runs-on: ubuntu-latest
+    name: Lint Python Sources
+    steps:
+      - name: Check out source repository
+        uses: actions/checkout@v3
+      - name: Set up Python environment
+        uses: actions/setup-python@v4
+        with:
+          python-version: "3.11"
+      - name: flake8 Lint
+        uses: py-actions/flake8@v2
+        with:
+          max-line-length: "100"
+
+  ######################
+  # Clang-Format Check #
+  ######################
+  # Check C/C++ files for correct formatting.
+  clangfmt:
+    name: Lint C/C++ Sources
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      - uses: DoozyX/clang-format-lint-action@v0.16.2
+        with:
+          clangFormatVersion: 10
+
+  ######################
+  # Lint Editor Config #
+  ######################
+  # Detect trailing whitespaces, missing new lines and wrong file encodings.
+  editorconfig-lint:
+    name: Lint Editorconfig
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      - uses: editorconfig-checker/action-editorconfig-checker@main
+      - run: editorconfig-checker
diff --git a/util/lint/.yamllint.yml b/util/lint/.yamllint.yml
@@ -0,0 +1,25 @@
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+extends: default
+
+rules:
+  document-start: disable
+  comments:
+    min-spaces-from-content: 1
+  line-length:
+    allow-non-breakable-words: true
+    allow-non-breakable-inline-mappings: true
+    ignore: |
+      Bender.yml
+      workflows/lint.yml
+  colons:
+    ignore: |
+      Bender.yml
+  braces:
+    ignore: |
+      Bender.yml
+  commas:
+    ignore: |
+      Bender.yml
diff --git a/util/lint/waiver.verible b/util/lint/waiver.verible
@@ -2,7 +2,7 @@
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #
-# waiver file for snitch_cluster lint
+# waiver file for occamy lint
 
 # Auto-generated by reggen, needs a more fundamental fix.
 waive --rule=line-length            --location="occamy_quadrant_s1_reg_top.sv"

diff --git a/util/occamygen/occamy.py b/util/occamygen/occamy.py
@@ -6,7 +6,7 @@
 from pathlib import Path
 
 sys.path.append(str(Path(__file__).parent / '../../deps/snitch_cluster/util/clustergen'))
-from cluster import Generator, PMA, PMACfg, SnitchCluster, clog2
+from cluster import Generator, PMA, PMACfg, SnitchCluster, clog2  # noqa: E402
 
 
 class Occamy(Generator):

diff --git a/util/occamygen/occamygen.py b/util/occamygen/occamygen.py
@@ -18,7 +18,7 @@
 from mako.template import Template
 
 sys.path.append(str(pathlib.Path(__file__).parent / '../'))
-from solder import solder, device_tree, util
+from solder import solder, device_tree, util  # noqa: E402
 
 # Compile a regex to trim trailing whitespaces on lines.
 re_trailws = re.compile(r'[ \t\r]+$', re.MULTILINE)
@@ -32,7 +32,8 @@ def write_template(tpl_path, outdir, fname=None, **kwargs):
         tpl_path = pathlib.Path(tpl_path).absolute()
         if tpl_path.exists():
             tpl = Template(filename=str(tpl_path))
-            fname = tpl_path.with_suffix("").name.replace("occamy", kwargs['args'].name) if not fname else fname
+            fname = tpl_path.with_suffix("").name.replace("occamy", kwargs['args'].name) \
+                if not fname else fname
             with open(outdir / fname, "w") as file:
                 code = tpl.render_unicode(**kwargs)
                 code = re_trailws.sub("", code)
@@ -359,8 +360,10 @@ def main():
     cluster_zero_mem_size = occamy.cfg["cluster"]["zero_mem_size"] * 1024
 
     # assert memory region allocation
-    error_str = "ERROR: cluster peripherals, zero memory and tcdm do not fit into the allocated memory region!!!"
-    assert (cluster_tcdm_size + cluster_periph_size + cluster_zero_mem_size) <= cluster_base_offset, error_str
+    error_str = "ERROR: cluster peripherals, zero memory and tcdm \
+                do not fit into the allocated memory region!!!"
+    assert (cluster_tcdm_size + cluster_periph_size + cluster_zero_mem_size) <= \
+           cluster_base_offset, error_str
 
     cluster_base_addr = occamy.cfg["cluster"]["cluster_base_addr"]
     quadrant_size = cluster_base_offset * nr_s1_clusters
@@ -417,7 +420,8 @@ def main():
         am.new_leaf(
                 "quad_{}_cfg".format(i),
                 occamy.cfg["s1_quadrant"]["cfg_base_offset"],
-                occamy.cfg["s1_quadrant"]["cfg_base_addr"] + i * occamy.cfg["s1_quadrant"]["cfg_base_offset"]
+                occamy.cfg["s1_quadrant"]["cfg_base_addr"] +
+                i * occamy.cfg["s1_quadrant"]["cfg_base_offset"]
             ).attach_to(
                 am_narrow_xbar_quadrant_s1[i]
             ).attach_to(
@@ -866,7 +870,8 @@ def main():
         "apb_hbm_cfg": apb_hbm_cfg,
         "cfg": occamy.cfg,
         "cores": nr_s1_quadrants * nr_s1_clusters * nr_cluster_cores + nr_remote_cores + 1,
-        "lcl_cores": nr_s1_quadrants * nr_s1_clusters * nr_cluster_cores + (0 if is_remote_quadrant else 1),
+        "lcl_cores": nr_s1_quadrants * nr_s1_clusters * nr_cluster_cores +
+        (0 if is_remote_quadrant else 1),
         "remote_quadrants": occamy.cfg["remote_quadrants"],
         "is_remote_quadrant": occamy.cfg["is_remote_quadrant"],
         "nr_s1_quadrants": nr_s1_quadrants,

diff --git a/util/solder/solder.py b/util/solder/solder.py
@@ -327,8 +327,8 @@ def emit(aw, dw, iw, uw):
         if key in AxiStruct.configs:
             return AxiStruct.configs[key]
         name = "axi_a{}_d{}_i{}_u{}".format(*key)
-        code = "// AXI bus with {} bit address, {} bit data, {} bit IDs, and {} bit user data.\n".format(
-            *key)
+        code = "// AXI bus with {} bit address, {} bit data, {} bit IDs, \
+            and {} bit user data.\n".format(*key)
         code += "`AXI_TYPEDEF_ALL_CT({}, {}_req_t, {}_resp_t, ".format(name, name, name)
         code += "logic [{}:0], logic [{}:0], logic [{}:0], logic [{}:0], logic [{}:0])\n".format(
             aw - 1, iw - 1, dw - 1, (dw + 7) // 8 - 1, max(0, uw - 1))
@@ -349,8 +349,8 @@ def emit(aw, dw):
         name = "axi_lite_a{}_d{}".format(*key)
         code = "// AXI-Lite bus with {} bit address and {} bit data.\n".format(
             *key)
-        code += "`AXI_LITE_TYPEDEF_ALL_CT({}, {}_req_t, {}_rsp_t, logic [{}:0], logic [{}:0], logic [{}:0])\n".format(
-            name, name, name, aw - 1, dw - 1, (dw + 7) // 8 - 1)
+        code += "`AXI_LITE_TYPEDEF_ALL_CT({}, {}_req_t, {}_rsp_t, logic [{}:0], logic [{}:0], \
+            logic [{}:0])\n".format(name, name, name, aw - 1, dw - 1, (dw + 7) // 8 - 1)
         code_package += "\n" + code
         AxiLiteStruct.configs[key] = name
         return name
@@ -678,8 +678,10 @@ def change_uw(self, context, target_uw, name, inst_name=None, to=None):
         # Emit the remapper instance.
         bus.declare(context)
         assgn = "// Change UW\n"
-        assgn += "`AXI_ASSIGN_REQ_STRUCT({lhs},{rhs})\n".format(lhs=bus.req_name(), rhs=self.req_name())
-        assgn += "`AXI_ASSIGN_RESP_STRUCT({lhs},{rhs})\n".format(lhs=self.rsp_name(), rhs=bus.rsp_name())
+        assgn += "`AXI_ASSIGN_REQ_STRUCT({lhs},{rhs})\n".format(lhs=bus.req_name(),
+                                                                rhs=self.req_name())
+        assgn += "`AXI_ASSIGN_RESP_STRUCT({lhs},{rhs})\n".format(lhs=self.rsp_name(),
+                                                                 rhs=bus.rsp_name())
         context.write(assgn)
         return bus