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fpga: 64-bits prefetchable BAR0
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CyrilKoe committed Mar 13, 2024
1 parent 3919dac commit cd80f79
Showing 1 changed file with 7 additions and 0 deletions.
7 changes: 7 additions & 0 deletions target/fpga/occamy_vcu128_bd.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -710,8 +710,15 @@ proc create_root_design { parentCell } {
CONFIG.axist_bypass_scale {Gigabytes} \
CONFIG.axist_bypass_size {4} \
CONFIG.axisten_freq {125} \
CONFIG.bar_indicator {BAR_1:0} \
CONFIG.functional_mode {AXI_Bridge} \
CONFIG.pf0_bar0_64bit {true} \
CONFIG.pf0_bar0_prefetchable {true} \
CONFIG.pf0_bar0_scale {Gigabytes} \
CONFIG.pf0_bar0_size {4} \
CONFIG.pf0_device_id {9014} \
CONFIG.pf0_msix_cap_pba_bir {BAR_1:0} \
CONFIG.pf0_msix_cap_table_bir {BAR_1:0} \
CONFIG.pl_link_cap_max_link_width {X4} \
CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \
CONFIG.xdma_axilite_slave {true} \
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