Merge remote-tracking branch 'origin/main' into rbarton/gemm

pulp-platform · Apr 1, 2024 · f8a02c5 · f8a02c5
2 parents 8ba104d + 4dbf9b4
commit f8a02c5
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diff --git a/.github/workflows/build-docker.yml b/.github/workflows/build-docker.yml
@@ -27,6 +27,6 @@ jobs:
           context: .
           file: util/container/Dockerfile
           push: true
-          tags: ghcr.io/pulp-platform/occamy:latest
+          tags: ghcr.io/pulp-platform/occamy:${{ github.ref_name }}
           build-args: |-
             SNITCH_LLVM_VERSION=latest
diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -15,7 +15,7 @@ jobs:
     name: Build documentation
     runs-on: ubuntu-22.04
     container:
-      image: ghcr.io/pulp-platform/occamy
+      image: ghcr.io/pulp-platform/occamy:main
     steps:
       - uses: actions/checkout@v2
       - name: Build docs
@@ -31,7 +31,7 @@ jobs:
     name: Build SW for Occamy
     runs-on: ubuntu-22.04
     container:
-      image: ghcr.io/pulp-platform/occamy
+      image: ghcr.io/pulp-platform/occamy:main
     steps:
       - uses: actions/checkout@v2
         with:
@@ -48,7 +48,7 @@ jobs:
     name: Generate Occamy RTL sources
     runs-on: ubuntu-22.04
     container:
-      image: ghcr.io/pulp-platform/occamy
+      image: ghcr.io/pulp-platform/occamy:main
     steps:
       - uses: actions/checkout@v2
         with:

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -5,32 +5,9 @@
 variables:
   GIT_STRATEGY: clone
   GIT_SUBMODULE_STRATEGY: recursive
-  PYTHON: /usr/local/anaconda3-2022.05/bin/python3
-  BENDER: bender-0.27.1
-  CLANG_FORMAT: clang-format-10.0.1
-  CC: gcc-9.2.0
-  CXX: g++-9.2.0
-  QUESTA_SEPP: questa-2022.3
-  LLVM_BINROOT: /usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin
-  CLANG: /usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin/clang
-  RISCV_GCC_VERSION: 8.3.0-2020.04.0
 
 before_script:
-  # yamllint disable rule:line-length
-  - $PYTHON -m venv .venv
-  - source .venv/bin/activate
-  - $BENDER update
-  - pip install -r python-requirements.txt
-  # Install CVA6 compiler toolchain
-  - curl -Ls -o riscv-gcc.tar.gz https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-$RISCV_GCC_VERSION-x86_64-linux-ubuntu14.tar.gz
-  - mkdir -p .tools/riscv && chmod 777 .tools/riscv
-  - tar -C .tools/riscv -xf riscv-gcc.tar.gz --strip-components=1
-  - export PATH="$(pwd)/.tools/riscv/bin:$PATH"
-  # Install verible
-  - mkdir -p .tools/verible && chmod 777 .tools/verible
-  - curl -L https://github.com/chipsalliance/verible/releases/download/v0.0-3222-gb19cdf44/verible-v0.0-3222-gb19cdf44-CentOS-7.9.2009-Core-x86_64.tar.gz | tar xz -C .tools/verible --strip-components=1
-  - export PATH="$(pwd)/.tools/verible/bin:$PATH"
-  # yamllint enable rule:line-length
+  source iis-setup.sh
 
 ##############
 # Build docs #
@@ -62,6 +39,6 @@ occamy-full-vsim:
   script:
     - cd target/sim
     - make CFG_OVERRIDE=cfg/full.hjson rtl
-    - make LENGTH=384 sw
+    - make sw
     - make bin/occamy_top.vsim
     - ./run.py sw/run-full-occamy.yaml --simulator vsim
diff --git a/Bender.yml b/Bender.yml
@@ -29,8 +29,9 @@ dependencies:
   cva6:                   { path: hw/vendor/openhwgroup_cva6                                                }
   opentitan_peripherals:  { path: hw/vendor/pulp_platform_opentitan_peripherals                             }
   register_interface:     { git:  https://github.com/pulp-platform/register_interface.git, version: 0.3.8   }
-  snitch_cluster:         { git:  https://github.com/pulp-platform/snitch_cluster.git,     rev:     8f8bf58ffa0e2cbee96d30a958da8c6bf53c07a8 }
+  snitch_cluster:         { git:  https://github.com/pulp-platform/snitch_cluster.git,     rev:     269830af872fa943d8b079470120d42d62e1cb69 }
   tech_cells_generic:     { git:  https://github.com/pulp-platform/tech_cells_generic.git, rev:     v0.2.11 }
+  cluster_icache:         { git:  https://github.com/pulp-platform/cluster_icache.git,     version: 0.1.0   }
 
 workspace:
   package_links:

diff --git a/hw/snitch_read_only_cache/src/snitch_read_only_cache.sv b/hw/snitch_read_only_cache/src/snitch_read_only_cache.sv
@@ -273,7 +273,7 @@ module snitch_read_only_cache #(
   );
 
   // The lookup module contains the actual cache RAMs and performs lookups.
-  snitch_icache_lookup #(
+  snitch_icache_lookup_parallel #(
     .CFG              ( CFG ),
     .sram_cfg_tag_t   ( sram_cfg_tag_t  ),
     .sram_cfg_data_t  ( sram_cfg_data_t )

diff --git a/iis-setup.sh b/iis-setup.sh
@@ -0,0 +1,32 @@
+#!/usr/bin/env bash
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+export BENDER=bender-0.27.1
+$BENDER checkout
+
+source deps/snitch_cluster/iis-setup.sh
+
+# TODO: uncomment if needed else remove
+# export CLANG=/usr/pack/riscv-1.0-kgf/pulp-llvm-0.12.0/bin/clang
+export CLANG_FORMAT=clang-format-10.0.1
+
+# Install CVA6 compiler toolchain
+RISCV_GCC_VERSION=8.3.0-2020.04.0
+mkdir -p tools/riscv
+chmod 777 tools/riscv
+cd tools/riscv
+curl -Ls -o riscv-gcc.tar.gz https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-$RISCV_GCC_VERSION-x86_64-linux-ubuntu14.tar.gz
+tar -xf riscv-gcc.tar.gz --strip-components=1
+export PATH=$(pwd)/bin:$PATH
+cd -
+
+# Install verible
+mkdir -p tools/verible
+chmod 777 tools/verible
+cd tools/verible
+curl -Ls -o verible.tar.gz https://github.com/chipsalliance/verible/releases/download/v0.0-3222-gb19cdf44/verible-v0.0-3222-gb19cdf44-CentOS-7.9.2009-Core-x86_64.tar.gz
+tar -xzf verible.tar.gz --strip-components=1
+export PATH=$(pwd)/bin:$PATH
+cd -
diff --git a/target/sim/Makefile b/target/sim/Makefile
@@ -15,17 +15,28 @@ CFG_OVERRIDE ?=     # Override default config file
 .DEFAULT_GOAL := help
 .PHONY: all clean
 all: rtl sw addrmap
-clean: clean-bender clean-rtl clean-sw clean-addrmap clean-vlt clean-vsim clean-vcs clean-logs
+clean: clean-bender clean-rtl clean-sw clean-addrmap clean-vlt clean-vcs clean-logs
 
 ############
 # Makefrag #
 ############
 
+# Common definitions used by included Makefiles
+
 MKFILE_PATH := $(abspath $(lastword $(MAKEFILE_LIST)))
 MKFILE_DIR  := $(dir $(MKFILE_PATH))
 ROOT        := $(MKFILE_DIR)../..
 SNITCH_ROOT := $(shell bender path snitch_cluster)
 
+TARGET = occamy_top
+
+CVA6_TXT_TRACE       = $(LOGS_DIR)/trace_hart_00000.txt
+CVA6_PERF_DUMP       = $(LOGS_DIR)/hart_00000_perf.json
+CVA6_ANNOTATED_TRACE = $(LOGS_DIR)/trace_hart_00000.s
+TXT_TRACES          += $(CVA6_TXT_TRACE)
+PERF_DUMPS          += $(CVA6_PERF_DUMP)
+ANNOTATED_TRACES    += $(CVA6_ANNOTATED_TRACE)
+
 include $(SNITCH_ROOT)/target/common/common.mk
 
 ############
@@ -190,13 +201,15 @@ test/bootrom.bin: test/bootrom.elf
 rtl: clint plic socctrl hbmctrl quadctrl soc tb
 clean-rtl: clean-clint clean-plic clean-socctrl clean-hbmctrl clean-quadctrl clean-soc clean-tb
 
-MISC_OCCAMYGEN_SV_TARGETS  = $(TARGET_SRC_DIR)/occamy_top.sv
-MISC_OCCAMYGEN_SV_TARGETS += $(TARGET_SRC_DIR)/occamy_soc.sv
-MISC_OCCAMYGEN_SV_TARGETS += $(TARGET_SRC_DIR)/occamy_pkg.sv
-MISC_OCCAMYGEN_SV_TARGETS += $(TARGET_SRC_DIR)/occamy_quadrant_s1.sv
-MISC_OCCAMYGEN_SV_TARGETS += $(TARGET_SRC_DIR)/occamy_quadrant_s1_ctrl.sv
-MISC_OCCAMYGEN_SV_TARGETS += $(TARGET_SRC_DIR)/occamy_xilinx.sv
-MISC_OCCAMYGEN_SV_TARGETS += $(TARGET_SRC_DIR)/occamy_cva6.sv
+MISC_OCCAMYGEN_SV_TEMPLATES  = $(SOURCE_OCCAMY_DIR)/occamy_top.sv.tpl
+MISC_OCCAMYGEN_SV_TEMPLATES += $(SOURCE_OCCAMY_DIR)/occamy_soc.sv.tpl
+MISC_OCCAMYGEN_SV_TEMPLATES += $(SOURCE_OCCAMY_DIR)/occamy_pkg.sv.tpl
+MISC_OCCAMYGEN_SV_TEMPLATES += $(SOURCE_OCCAMY_DIR)/occamy_quadrant_s1.sv.tpl
+MISC_OCCAMYGEN_SV_TEMPLATES += $(SOURCE_OCCAMY_DIR)/occamy_quadrant_s1_ctrl.sv.tpl
+MISC_OCCAMYGEN_SV_TEMPLATES += $(SOURCE_OCCAMY_DIR)/occamy_xilinx.sv.tpl
+MISC_OCCAMYGEN_SV_TEMPLATES += $(SOURCE_OCCAMY_DIR)/occamy_cva6.sv.tpl
+
+MISC_OCCAMYGEN_SV_TARGETS  = $(addprefix $(TARGET_SRC_DIR)/,$(notdir $(basename $(MISC_OCCAMYGEN_SV_TEMPLATES))))
 MISC_OCCAMYGEN_SV_TARGETS += $(TARGET_SRC_DIR)/occamy_cluster_wrapper.sv
 
 MISC_OCCAMYGEN_TARGETS  = $(MISC_OCCAMYGEN_SV_TARGETS)
@@ -207,7 +220,7 @@ clean-soc:
 	rm -rf $(MISC_OCCAMYGEN_TARGETS) .misc_occamygen_targets_group
 
 $(MISC_OCCAMYGEN_TARGETS): .misc_occamygen_targets_group
-.misc_occamygen_targets_group: $(CFG)
+.misc_occamygen_targets_group: $(CFG) $(MISC_OCCAMYGEN_SV_TEMPLATES)
 	@echo "[OCCAMYGEN] Generate $(MISC_OCCAMYGEN_TARGETS)"
 	@$(OCCAMYGEN) --cfg $(CFG) --outdir $(TARGET_SRC_DIR)\
 		--wrapper \
@@ -505,56 +518,41 @@ $(VLT_BUILDDIR)/test/uartdpi/uartdpi.o: test/uartdpi/uartdpi.c
 	$(CC) $(CFLAGS) $(VLT_CFLAGS) -c $< -o $@
 
 # Link verilated archive wich $(VLT_COBJ)
-$(BIN_DIR)/occamy_top.vlt: $(VLT_AR) $(VLT_COBJ) ${VLT_BUILDDIR}/lib/libfesvr.a
+$(BIN_DIR)/$(TARGET).vlt: $(VLT_AR) $(VLT_COBJ) ${VLT_BUILDDIR}/lib/libfesvr.a
 	mkdir -p $(dir $@)
 	$(CXX) $(LDFLAGS) -std=c++14 -L ${VLT_BUILDDIR}/lib -o $@ $(VLT_COBJ) $(VLT_AR) -lfesvr -lpthread -lutil
 
 # Clean all build directories and temporary files for Verilator simulation
 .PHONY: clean-vlt
 clean-vlt: clean-work
 	rm -rf work-vlt
-	rm -f $(BIN_DIR)/occamy_top.vlt
+	rm -f $(BIN_DIR)/$(TARGET).vlt
 
 ############
-# Modelsim #
+# Questasim #
 ############
 
-${VSIM_BUILDDIR}/compile.vsim.tcl: $(VSIM_SOURCES) ${TB_SRCS} ${TB_CC_SOURCES} test/bootrom.bin | $(VSIM_BUILDDIR)
-	$(VLIB) $(dir $@)
-	${BENDER} script vsim ${VSIM_BENDER} --vlog-arg="${VLOG_FLAGS} -work $(dir $@) " > $@
-	echo '${VLOG} -work $(dir $@) $(TB_CC_SOURCES) -ccflags "$(TB_CC_FLAGS)"' >> $@
-	echo 'return 0' >> $@
-
-# Build compilation script and compile all sources for Questasim simulation
-$(BIN_DIR)/occamy_top.vsim: ${VSIM_BUILDDIR}/compile.vsim.tcl work/lib/libfesvr.a | ${VSIM_BUILDDIR}
-	$(call QUESTASIM,tb_bin)
-	@# Rename CVA6 trace to align with Snitch trace names
-	@echo "mv ${CVA6_TRACE} $(LOGS_DIR)/trace_hart_00000.txt" >> $@
-	@echo "mv ${CVA6_TRACE} $(LOGS_DIR)/trace_hart_00000.txt" >> $@.gui
-	@# Move all other traces to logs folder as well
-	@echo "mv *trace*.log $(LOGS_DIR)/" >> $@
-	@echo "mv *trace*.log $(LOGS_DIR)/" >> $@.gui
-
-# Clean all build directories and temporary files for Questasim simulation
-clean-vsim: clean-work
-	rm -rf $(BIN_DIR)/occamy_top.vsim $(BIN_DIR)/occamy_top.vsim.gui $(VSIM_BUILDDIR) vsim.wlf
+include $(SNITCH_ROOT)/target/common/vsim.mk
+
+# Add dependency on bootrom
+$(BIN_DIR)/$(TARGET).vsim: test/bootrom.bin
 
 #######
 # VCS #
 #######
 
 # Build compilation script and compile all sources for VCS simulation
-$(BIN_DIR)/occamy_top.vcs: work-vcs/compile.sh work/lib/libfesvr.a ${TB_CC_SOURCES} test/bootrom.bin
+$(BIN_DIR)/$(TARGET).vcs: work-vcs/compile.sh work/lib/libfesvr.a ${TB_CC_SOURCES} test/bootrom.bin
 	mkdir -p bin
-	vcs $(VCS_FLAGS) -o $(BIN_DIR)/occamy_top.vcs tb_bin -cc $(CC) -cpp $(CXX) \
+	vcs $(VCS_FLAGS) -o $(BIN_DIR)/$(TARGET).vcs tb_bin -cc $(CC) -cpp $(CXX) \
 		$(TB_CC_SOURCES) -CFLAGS "$(TB_CC_FLAGS)" -LDFLAGS "-L${FESVR}/lib" -lfesvr -lutil
 
 # Clean all build directories and temporary files for VCS simulation
 .PHONY: clean-vcs
 clean-vcs: clean-work
 	rm -rf AN.DB
 	rm -rf work-vcs
-	rm -f $(BIN_DIR)/occamy_top.vcs
+	rm -f $(BIN_DIR)/$(TARGET).vcs
 
 ########
 # FPGA #
@@ -575,7 +573,7 @@ clean-work:
 	rm -rf work
 
 clean-bender:
-	rm -rf $(ROOT)/Bender.lock $(ROOT)/.bender/ $(ROOT)/deps
+	rm -rf $(BENDER_LOCK) $(ROOT)/.bender/ $(ROOT)/deps
 
 clean-logs:
 	rm -rf $(LOGS_DIR)/
@@ -589,9 +587,9 @@ help:
 	@echo -e ""
 	@echo -e "${Blue}help           ${Black}Show an overview of all Makefile targets."
 	@echo -e ""
-	@echo -e "${Blue}bin/occamy_top.vcs  ${Black}Build compilation script and compile all sources for VCS simulation. @IIS: vcs-2020.12 make bin/occamy_top.vcs"
-	@echo -e "${Blue}bin/occamy_top.vlt  ${Black}Build compilation script and compile all sources for Verilator simulation."
-	@echo -e "${Blue}bin/occamy_top.vsim ${Black}Build compilation script and compile all sources for Questasim simulation. @IIS: QUESTA_HOME=/usr/pack/modelsim-10.7b-kgf/questasim/ CC=$(QUESTA_HOME)/gcc-5.3.0-linux_x86_64/bin/gcc CXX=$(QUESTA_HOME)/gcc-5.3.0-linux_x86_64/bin/g++ LD=$(QUESTA_HOME)/gcc-5.3.0-linux_x86_64/bin/ld make bin/occamy_top.vsim"
+	@echo -e "${Blue}bin/$(TARGET).vcs  ${Black}Build compilation script and compile all sources for VCS simulation. @IIS: vcs-2020.12 make bin/$(TARGET).vcs"
+	@echo -e "${Blue}bin/$(TARGET).vlt  ${Black}Build compilation script and compile all sources for Verilator simulation."
+	@echo -e "${Blue}bin/$(TARGET).vsim ${Black}Build compilation script and compile all sources for Questasim simulation. @IIS: QUESTA_HOME=/usr/pack/modelsim-10.7b-kgf/questasim/ CC=$(QUESTA_HOME)/gcc-5.3.0-linux_x86_64/bin/gcc CXX=$(QUESTA_HOME)/gcc-5.3.0-linux_x86_64/bin/g++ LD=$(QUESTA_HOME)/gcc-5.3.0-linux_x86_64/bin/ld make bin/$(TARGET).vsim"
 	@echo -e ""
 	@echo -e "${Blue}all            ${Black}Update all SW and HW related sources (by, e.g., re-generating the RegGen registers and their c-header files)."
 	@echo -e "${Blue}fpga           ${Black}Build a small Occamy version (CVA6 + 1xcluster) for the VCU128 FPGA board."

diff --git a/target/sim/run.py b/target/sim/run.py
@@ -20,10 +20,9 @@
 
 def main():
     args = parser('vsim', SIMULATORS.keys()).parse_args()
-    simulations = get_simulations(args.testlist, SIMULATORS[args.simulator])
+    simulations = get_simulations(args.testlist, SIMULATORS[args.simulator], run_dir=args.run_dir)
     return run_simulations(simulations,
                            n_procs=args.n_procs,
-                           run_dir=Path(args.run_dir),
                            dry_run=args.dry_run,
                            early_exit=args.early_exit)
 

diff --git a/target/sim/sw/device/runtime/src/occamy_start.c b/target/sim/sw/device/runtime/src/occamy_start.c
@@ -10,12 +10,22 @@
 #define SNRT_CRT0_PRE_BARRIER
 #define SNRT_INVOKE_MAIN
 #define SNRT_CRT0_POST_BARRIER
-#define SNRT_CRT0_CALLBACK7
+#define SNRT_CRT0_EXIT
+#define SNRT_CRT0_ALTERNATE_EXIT
 
 static inline void snrt_crt0_callback3() {
     _snrt_cluster_hw_barrier = cluster_hw_barrier_addr(snrt_cluster_idx());
 }
 
-static inline void snrt_crt0_callback7() { return_to_cva6(SYNC_CLUSTERS); }
+static inline uint32_t* snrt_exit_code_destination() {
+    return soc_ctrl_scratch_ptr(3);
+}
+
+static inline void snrt_exit_default(int exit_code);
+
+static inline void snrt_exit(int exit_code) {
+    snrt_exit_default(exit_code);
+    if (snrt_global_core_idx() == 0) set_host_sw_interrupt();
+}
 
 #include "start.c"
diff --git a/target/sim/sw/host/apps/offload/src/offload.c b/target/sim/sw/host/apps/offload/src/offload.c
@@ -15,12 +15,13 @@ int main() {
     // Program Snitch entry point and communication buffer
     program_snitches();
 
+    // Compiler fence to ensure Snitch entry point is
+    // programmed before Snitches are woken up
+    asm volatile("" ::: "memory");
+
     // Start Snitches
     wakeup_snitches_cl();
 
-    // Wait for job done
-    wait_snitches_done();
-
-    // Exit routine
-    mcycle();
+    // Wait for job done and return Snitch exit code
+    return wait_snitches_done();
 }
diff --git a/target/sim/sw/host/runtime/host.c b/target/sim/sw/host/runtime/host.c
@@ -90,6 +90,16 @@ void initialize_bss() {
                            bss_size);
 }
 
+void initialize_wide_spm() {
+    extern volatile uint64_t __wide_spm_start, __wide_spm_end;
+
+    size_t wide_spm_size =
+        (size_t)(&__wide_spm_end) - (size_t)(&__wide_spm_start);
+    if (wide_spm_size)
+        sys_dma_blk_memcpy(SPM_WIDE_BASE_ADDR, (uint64_t)(&__wide_spm_start),
+                           wide_spm_size);
+}
+
 void enable_fpu() {
     uint64_t mstatus;
 
@@ -258,9 +268,15 @@ void wakeup_master_snitches() {
 /**
  * @brief Waits until snitches are done executing
  */
-static inline void wait_snitches_done() {
+static inline int wait_snitches_done() {
     wait_sw_interrupt();
     clear_host_sw_interrupt();
+    int retval = *soc_ctrl_scratch_ptr(3);
+    // LSB signals completion
+    if (retval & 1)
+        return retval >> 1;
+    else
+        return -1;
 }
 
 static inline volatile uint32_t* get_shared_lock() {

diff --git a/target/sim/sw/host/runtime/host.ld b/target/sim/sw/host/runtime/host.ld
@@ -41,6 +41,15 @@ SECTIONS
     __bss_end = . ;
   } > DRAM
 
+  .wide_spm :
+  {
+    . = ALIGN(8);
+    __wide_spm_start = . ;
+    *(.wide_spm)
+    . = ALIGN(8);
+    __wide_spm_end = . ;
+  } > DRAM
+
   __end = .;
 
   .devicebin : { *(.devicebin) } > DRAM

diff --git a/target/sim/sw/host/runtime/start.S b/target/sim/sw/host/runtime/start.S
@@ -43,6 +43,7 @@ _start:
     la      gp, __global_pointer$
     .option pop
     call initialize_bss
+    call initialize_wide_spm
     call enable_fpu
     call main