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occamy: Update register interface and peripherals #207

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@paulsc96 paulsc96 commented Aug 18, 2021

This PR

  • Updates register_interface and therefore our fork of the regtool.py generator and regenerates existing regfiles.
  • Updates and appropriately repatches the OpenTitan peripherals we use, most notably adding a non-stubbed SPI.
  • Replaces the non-16550-conform OpenTitan UART with an existing SV port of the 16550-conform VHDL pulp_platform/apb_uart as used in CVA6.

So far, only basic issues have been ruled out; Occamy compiles and simulates. It will be ready to merge once:

  • All peripherals needed to boot have been verified to work in a bare-metal Occamy boot ROM:
    • UART
    • SPI
    • I2C
  • The Occamy device tree was updated with the new UART
  • The PLIC and new driver-compliant UART have been shown to work with Linux in Occamy FPGA simulation (@niwis) (delegated to occamy: FPGA Linux boot hangs on init process #251).

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niwis commented Sep 9, 2021

The good news: the UART seems to be working! 🎉
The bad news: Linux does not boot anymore. This is the last output:

[   37.982674] Freeing unused kernel memory: 7928K
[   37.993771] This architecture does not have kernel memory protection.
[   38.009054] Run /init as init process
[   48.006306] random: dd: uninitialized urandom read (512 bytes read)
[  261.893203] random: crng init done

After that, Linux eventually loops in kernel space. To me, it looks like busybox is for some reason not able to access the console. This can be a SW issue (the Linux image is unchanged, though), or it could be related to some of the HW changes. The ILA suggests that busybox init is correctly called and executed, but the control path quickly becomes untracable.

Regarding next debugging steps: follow this busybox FAQ: https://busybox.net/FAQ.html#init
If hello world does not print, we should be able to pinpoint the issue using gdb / the ILA.

Update code from upstream repository https://github.com/pulp-
platform/register_interface.git to revision
73de8e51b79f416350229b1d2420b2c527e002b8

* Release v0.3.1 (Manuel Eggimann)
* Update README (Manuel Eggimann)
* Align axi version in ips_list with Bender.yml (Manuel Eggimann)
* Release v0.3.0 (Manuel Eggimann)
* Bump AXI version (Manuel Eggimann)
* Update changelog (Manuel Eggimann)
* Rebased reggen patches on top of current master (Manuel Eggimann)
* Release v0.2.2 (Florian Zaruba)
* Bump axi version (#12) (Manuel Eggimann)
* ci: Also run on pull requests (#11) (Florian Zaruba)
* Add periph to register adapter (#10) (Michael Rogenmoser)
* Release v0.2.1 (Florian Zaruba)
* src_files.yml: Remove dropped pkg (bluew)
* Update axi and common_cells dependencies (#9) (Michael Rogenmoser)
* Add reggen register primitives to src_files.yml (Manuel Eggimann)
* Add ip_description for IPAppprox (Manuel Eggimann)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

python-requirements: Add yaml package
paulsc96 and others added 13 commits September 15, 2021 14:12
snitch_cluster: Remove non-existant DE connection in cluster peripherals
Update code from upstream repository
https://github.com/lowRISC/opentitan.git to revision
726718a6de32aa047a4064e02e7b619699f054ed

* [dv/prim_esc] Fix prim_esc regression error (Cindy Chen)
* [spi_host,design] Properly handle TX "stall" and "flush" conditions
  (Martin Lueker-Boden)
* [sram_ctrl] Harden initialization counter (Michael Schaffner)
* [fpv/rv_plic] Fix assertion irq_id_o width (Cindy Chen)
* [prim] SRAM Async FIFO (Eunchan Kim)
* [prim_lfsr] Do not shadow |state| variable (Philipp Wagner)
* [prim] Add non-linear out option to prim_lfsr (Timothy Chen)
* [primgen] Instantiate tech libs in stable order (Philipp Wagner)
* [primgen] Actually find the Verible Python wrapper (Philipp Wagner)
* [dv/prim_esc] fix regression error (Cindy Chen)
* [dv/gpio] fix intr_test regression failure (Cindy Chen)
* [dv/common] Exclude assertion coverage from IP level testbench
  (Cindy Chen)
* [i2c, rtl] Update i2c.prj.hjson for D2 completion (Igor Kouznetsov)
* [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda)
* [sram_ctrl] Update docs (Michael Schaffner)
* [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner)
* [dv/gpio] Fix filter_stress test timeout (Cindy Chen)
* [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen)
* [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen)
* [dv/ips] Fix a few small items in gpio and hmac (Cindy Chen)
* [prim_xor2/lint] Add waiver for .* use in generated prim (Michael
  Schaffner)
* [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer)
* [util, reggen] Support standardized cdc handling for regfile
  (Timothy Chen)
* [spi_host/dv] updated checkout list to track doc and testplan status
  (Rasmus Madsen)
* [spi_host/dv/doc] Updated dv plan for spi host for V1 review (Rasmus
  Madsen)
* [spi_host/dv/doc] Updated spi_host testplan (Rasmus Madsen)
* [i2c, doc] Checklist Update for D2 Sign-off (Igor Kouznetsov)
* [rtl/prim_alert_sender] Allow ping_req to stay high without error
  (Cindy Chen)
* [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen)
* [prim_subreg_shadow] Make local parameter a localparam (Philipp
  Wagner)
* [prim_subreg] Make software access type an enum (Philipp Wagner)
* [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen)
* [edn] Add MaxLatency assertion (Eunchan Kim)
* [prim_subreg_shadow] Correct write data signal usage (Michael
  Schaffner)
* [prim_lfsr] Fix assertion issue occuring right after reset (Michael
  Schaffner)
* [memutil] Allow use without scrambled memories (Philipp Wagner)
* [prim_prince] Fix comment (Philipp Wagner)
* [memutil] Fix width mismatch (Philipp Wagner)
* [prim] Allow disabling SVAs ensuring REQ is held until ACK at run
  time (Pirmin Vogel)
* [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen)
* [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert
  Swarbrick)
* [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs
  (Michael Schaffner)
* [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug
  (Michael Schaffner)
* [primgen] Remove unused import (Philipp Wagner)
* [primgen] Add shebang (Philipp Wagner)
* [primgen] Make primgen "portable" again (Philipp Wagner)
* [rv_plic] rv_plic updates as part of rv_core_ibex templating
  (Timothy Chen)
* [ spi_host ] Fix Lint Errors (Martin Lueker-Boden)
* [fpv/rv_plic] Fix compile error with alert (Cindy Chen)
* [uart] Minor lint fix (Timothy Chen)
* [ spi_host ] Transition to D1 (Martin Lueker-Boden)
* [spi_host,doc] Update spi_host documentation (Martin Lueker-Boden)
* [pwm, dv] Fix fifo test for i2c host rtl (Tung Hoang)
* [dv/uart] Fix assertion (Weicai Yang)
* [doc/fpv] Unify the wording for IPs that verified in FPV (Cindy
  Chen)
* [reggen] Pair up clock and reset signals (Rupert Swarbrick)
* [integ alerts] Align description of integ alerts (Michael Schaffner)
* [tlul] Add some missing dependencies (Michael Schaffner)
* [rv_plic] Fix a bitwidth lint error (Michael Schaffner)
* [rv_plic] Wire up integ alert (Michael Schaffner)
* [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael
  Schaffner)
* [spi*/uart] Make sure integ alert is fatal (Michael Schaffner)
* [adc_ctrl] Various preparation steps for d2 (Timothy Chen)
* [dv/i2c] Fix alert clock/reset (Weicai Yang)
* [i2c, rtl] FIFO Depth Parameterization (Igor Kouznetsov)
* Revert "[prim] Do remove prim_esc.core from the dependencies"
  (Rupert Swarbrick)
* [prim] Remove dependency of prim:esc on a hardware block (Rupert
  Swarbrick)
* [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick)
* [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick)
* [dv] Add C++ memory scrambling model (Greg Chadwick)
* [prim] Do remove prim_esc.core from the dependencies (Michael
  Schaffner)
* [i2c, doc] Updated Description of Clock Stretching by Target (Igor
  Kouznetsov)
* [reggen] Generate a single we/re signal per register in reg_top
  (Rupert Swarbrick)
* [alert_handler] Implement reverse ping feature (Michael Schaffner)
* [prim_esc] Split the prims into their own core file (Michael
  Schaffner)
* [uart/dv] Fix regression failure (Weicai Yang)
* [dv/common] Stress_all_with_rand_reset apply reset concurrently
  (Cindy Chen)
* [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda)
* [i2c, rtl] Lint fixes (Igor Kouznetsov)
* [reggen] Simplify reg_top ports if there's exactly one window
  (Rupert Swarbrick)
* [prim_fifo_async] Fix a width calculation issue in case of Depth = 1
  (Michael Schaffner)
* [dv] Add automated alert_test to all IPs with new tl_int alert
  (Cindy Chen)
* [i2c] Wire up integrity alert (Michael Schaffner)
* [uart/dv] reduce sim time for smoke test (Weicai Yang)
* [i2c, rtl] Lint Fixes (Igor Kouznetsov)
* [dv/stress_all_with_reset] Revert back IPs that uses apply_reset
  (Cindy Chen)
* [uart] Wire up integrity alert (Michael Schaffner)
* [gpio] Wire up bus integrity alert (Michael Schaffner)
* [i2c, dv] Fix csr_* and smoke test for I2C (Tung Hoang)
* [gpio/dv] add run-opt for gpio_tl_intg_err (Weicai Yang)
* [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy
  Chen)
* [reggen] Make spacing uniform and simplify comments in reg_top
  (Rupert Swarbrick)
* [spi_host] Wire up integrity alert (Michael Schaffner)
* [uart/dv] Fix unmapped test (Weicai Yang)
* [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner)
* [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops
  (Michael Schaffner)
* [i2c, rtl] Fixes to Lint Errors and Changes to Clock Stretching by
  Target (Igor Kouznetsov)
* [doc, testplans] Fix non-existent tests (Srikrishna Iyer)
* [i2c, rtl] Loopback test and other changes (Igor Kouznetsov)
* [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki)
* [rv_plic] fix Src width mismatch (Eunchan Kim)
* [prim] Break always_comb block to avoid apparent loop (Rupert
  Swarbrick)
* [fpv] update secded_gen (Cindy Chen)
* [dv/common] Improve coverage exclusion method (Cindy Chen)
* [dvsim] Testplanner refactor & covergroup support (Srikrishna Iyer)
* [otp_ctrl] Workaround for generated prim depending on generated prim
  (Michael Schaffner)
* [checklists] Update all checklists for consistency (Srikrishna Iyer)
* [prim_secded] Add C reference models for Hsiao encode (Greg
  Chadwick)
* [rtl/prim_async_fifo] Fix async fifo typo when depth <= 2 (Cindy
  Chen)
* [pads] - added AnalogIn1 pads for OTP supply (Arnon Sharlin)
* [dv/common] add ECC support to mem_bkdr_if (Udi Jonnalagadda)
* [prim_secded] Use _i/_o suffix for port names (Philipp Wagner)
* [prim_fifo_async] Style fixes (Philipp Wagner)
* [uart] Fix line continuation in DV code (Philipp Wagner)
* Remove non-ASCII characters from SV code and meson.build (Rupert
  Swarbrick)
* [ spi_host ] Remove cmd_len_q register to clean up DC logs (Martin
  Lueker-Boden)
* [fpv/spi_host] Fix undecleared variable issue (Cindy Chen)
* [ spi_device, spi_host, top_earlgrey ] Add SPI passthrough to
  spi_host (Martin Lueker-Boden)
* [uart,lint] Waive warning about unused field in uart reg2hw (Rupert
  Swarbrick)
* [ prim ] Suppress unneeded assertion when clearing prim_packer_fifo
  (Martin Lueker-Boden)
* [spi_host] Proper routing of sd_o in standard mode. (Martin Lueker-
  Boden)
* [all] Minor lint fixes (Timothy Chen)
* [regtool] Reformulate wr_err calculation to avoid long lines (Rupert
  Swarbrick)
* [prim_clock_div] Update waiver (Michael Schaffner)
* [prim] Make SECDED prim generation deterministic (Rupert Swarbrick)
* [prim_pad_attr/prim_flop_en] Add waiver files (Michael Schaffner)
* [spi_host] Minor lint fixes (Michael Schaffner)
* [prim_clock_div] Update waiver file (Michael Schaffner)
* [top] change prim_generic usage into prim (Timothy Chen)
* Add formatting changes from allow list (Rafal Kapuscik)
* [prim] Add generic and Xilinx-specific xor2 primitives (Pirmin
  Vogel)
* [prim] Add generic and Xilinx-specific enable-FF primitives (Pirmin
  Vogel)
* [ spi_host ] SPI_HOST Implementation (Martin Lueker-Boden)
* [pinmux/padring] Wire up the pad attribute WARL behavior modules
  (Michael Schaffner)
* [pad_wrapper] Extend the generic and Xilinx pad wrapper models
  (Michael Schaffner)
* [dv] Update scb for all blocks (Weicai Yang)
* [prim_arbiter,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [rv_plic,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [prim] Fix lint warnings, replace inline AscentLint waivers (Pirmin
  Vogel)
* [dv] Update `process_tl_access` args for all blocks (Weicai Yang)
* [formal] Clean up some formal warnings (Cindy Chen)
* [topgen] Rework pinmux datastructure and templatize tops (Michael
  Schaffner)
* [prim_fifo_async] Make async FIFO output zero when empty (Noah
  Moroze)
* [ci] Switch from a blacklist to a whitelist for executable files
  (Rupert Swarbrick)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>
vendor: Update SPI patches
* Remove the Xilinx UART from the Block Design
* Map internal UART to UART0 of VCU128
* Update device tree
* Update ZSBL

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
@paulsc96
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Since the updated regtool and peripherals are blocking a number of things, we will fast-track this PR and address the init issue (#251) in another PR.

@paulsc96 paulsc96 marked this pull request as ready for review September 15, 2021 12:36
@paulsc96 paulsc96 merged commit fb30fb2 into master Sep 15, 2021
@paulsc96 paulsc96 deleted the update/periphs branch September 15, 2021 13:13
@niwis niwis restored the update/periphs branch October 6, 2021 09:42
@paulsc96 paulsc96 deleted the update/periphs branch January 18, 2022 14:06
paulsc96 added a commit to pulp-platform/snitch_cluster that referenced this pull request Jul 11, 2023
…ch#207)

* vendor: Prevent recursive vendor patching of `register_interface`

* vendor: Update pulp_platform_register_interface to 73de8e5

Update code from upstream repository https://github.com/pulp-
platform/register_interface.git to revision
73de8e51b79f416350229b1d2420b2c527e002b8

* Release v0.3.1 (Manuel Eggimann)
* Update README (Manuel Eggimann)
* Align axi version in ips_list with Bender.yml (Manuel Eggimann)
* Release v0.3.0 (Manuel Eggimann)
* Bump AXI version (Manuel Eggimann)
* Update changelog (Manuel Eggimann)
* Rebased reggen patches on top of current master (Manuel Eggimann)
* Release v0.2.2 (Florian Zaruba)
* Bump axi version (pulp-platform/snitch#12) (Manuel Eggimann)
* ci: Also run on pull requests (pulp-platform/snitch#11) (Florian Zaruba)
* Add periph to register adapter (pulp-platform/snitch#10) (Michael Rogenmoser)
* Release v0.2.1 (Florian Zaruba)
* src_files.yml: Remove dropped pkg (bluew)
* Update axi and common_cells dependencies (pulp-platform/snitch#9) (Michael Rogenmoser)
* Add reggen register primitives to src_files.yml (Manuel Eggimann)
* Add ip_description for IPAppprox (Manuel Eggimann)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

python-requirements: Add yaml package

* vendor: Patch windowing bug in pulp_platform regtool

* vendor: Add regtool patch

* snitch_cluster: Regenerate peripheral registers with new generator

snitch_cluster: Remove non-existant DE connection in cluster peripherals

* occamy: Regenerate CLINT register interface

* occamy: Regenerate SoC registers

* vendor: Exclude unneeded files from opentitan vendor, remove UART

* vendor: Update lowrisc_opentitan to lowRISC/opentitan@726718a6d

Update code from upstream repository
https://github.com/lowRISC/opentitan.git to revision
726718a6de32aa047a4064e02e7b619699f054ed

* [dv/prim_esc] Fix prim_esc regression error (Cindy Chen)
* [spi_host,design] Properly handle TX "stall" and "flush" conditions
  (Martin Lueker-Boden)
* [sram_ctrl] Harden initialization counter (Michael Schaffner)
* [fpv/rv_plic] Fix assertion irq_id_o width (Cindy Chen)
* [prim] SRAM Async FIFO (Eunchan Kim)
* [prim_lfsr] Do not shadow |state| variable (Philipp Wagner)
* [prim] Add non-linear out option to prim_lfsr (Timothy Chen)
* [primgen] Instantiate tech libs in stable order (Philipp Wagner)
* [primgen] Actually find the Verible Python wrapper (Philipp Wagner)
* [dv/prim_esc] fix regression error (Cindy Chen)
* [dv/gpio] fix intr_test regression failure (Cindy Chen)
* [dv/common] Exclude assertion coverage from IP level testbench
  (Cindy Chen)
* [i2c, rtl] Update i2c.prj.hjson for D2 completion (Igor Kouznetsov)
* [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda)
* [sram_ctrl] Update docs (Michael Schaffner)
* [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner)
* [dv/gpio] Fix filter_stress test timeout (Cindy Chen)
* [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen)
* [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen)
* [dv/ips] Fix a few small items in gpio and hmac (Cindy Chen)
* [prim_xor2/lint] Add waiver for .* use in generated prim (Michael
  Schaffner)
* [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer)
* [util, reggen] Support standardized cdc handling for regfile
  (Timothy Chen)
* [spi_host/dv] updated checkout list to track doc and testplan status
  (Rasmus Madsen)
* [spi_host/dv/doc] Updated dv plan for spi host for V1 review (Rasmus
  Madsen)
* [spi_host/dv/doc] Updated spi_host testplan (Rasmus Madsen)
* [i2c, doc] Checklist Update for D2 Sign-off (Igor Kouznetsov)
* [rtl/prim_alert_sender] Allow ping_req to stay high without error
  (Cindy Chen)
* [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen)
* [prim_subreg_shadow] Make local parameter a localparam (Philipp
  Wagner)
* [prim_subreg] Make software access type an enum (Philipp Wagner)
* [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen)
* [edn] Add MaxLatency assertion (Eunchan Kim)
* [prim_subreg_shadow] Correct write data signal usage (Michael
  Schaffner)
* [prim_lfsr] Fix assertion issue occuring right after reset (Michael
  Schaffner)
* [memutil] Allow use without scrambled memories (Philipp Wagner)
* [prim_prince] Fix comment (Philipp Wagner)
* [memutil] Fix width mismatch (Philipp Wagner)
* [prim] Allow disabling SVAs ensuring REQ is held until ACK at run
  time (Pirmin Vogel)
* [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen)
* [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert
  Swarbrick)
* [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs
  (Michael Schaffner)
* [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug
  (Michael Schaffner)
* [primgen] Remove unused import (Philipp Wagner)
* [primgen] Add shebang (Philipp Wagner)
* [primgen] Make primgen "portable" again (Philipp Wagner)
* [rv_plic] rv_plic updates as part of rv_core_ibex templating
  (Timothy Chen)
* [ spi_host ] Fix Lint Errors (Martin Lueker-Boden)
* [fpv/rv_plic] Fix compile error with alert (Cindy Chen)
* [uart] Minor lint fix (Timothy Chen)
* [ spi_host ] Transition to D1 (Martin Lueker-Boden)
* [spi_host,doc] Update spi_host documentation (Martin Lueker-Boden)
* [pwm, dv] Fix fifo test for i2c host rtl (Tung Hoang)
* [dv/uart] Fix assertion (Weicai Yang)
* [doc/fpv] Unify the wording for IPs that verified in FPV (Cindy
  Chen)
* [reggen] Pair up clock and reset signals (Rupert Swarbrick)
* [integ alerts] Align description of integ alerts (Michael Schaffner)
* [tlul] Add some missing dependencies (Michael Schaffner)
* [rv_plic] Fix a bitwidth lint error (Michael Schaffner)
* [rv_plic] Wire up integ alert (Michael Schaffner)
* [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael
  Schaffner)
* [spi*/uart] Make sure integ alert is fatal (Michael Schaffner)
* [adc_ctrl] Various preparation steps for d2 (Timothy Chen)
* [dv/i2c] Fix alert clock/reset (Weicai Yang)
* [i2c, rtl] FIFO Depth Parameterization (Igor Kouznetsov)
* Revert "[prim] Do remove prim_esc.core from the dependencies"
  (Rupert Swarbrick)
* [prim] Remove dependency of prim:esc on a hardware block (Rupert
  Swarbrick)
* [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick)
* [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick)
* [dv] Add C++ memory scrambling model (Greg Chadwick)
* [prim] Do remove prim_esc.core from the dependencies (Michael
  Schaffner)
* [i2c, doc] Updated Description of Clock Stretching by Target (Igor
  Kouznetsov)
* [reggen] Generate a single we/re signal per register in reg_top
  (Rupert Swarbrick)
* [alert_handler] Implement reverse ping feature (Michael Schaffner)
* [prim_esc] Split the prims into their own core file (Michael
  Schaffner)
* [uart/dv] Fix regression failure (Weicai Yang)
* [dv/common] Stress_all_with_rand_reset apply reset concurrently
  (Cindy Chen)
* [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda)
* [i2c, rtl] Lint fixes (Igor Kouznetsov)
* [reggen] Simplify reg_top ports if there's exactly one window
  (Rupert Swarbrick)
* [prim_fifo_async] Fix a width calculation issue in case of Depth = 1
  (Michael Schaffner)
* [dv] Add automated alert_test to all IPs with new tl_int alert
  (Cindy Chen)
* [i2c] Wire up integrity alert (Michael Schaffner)
* [uart/dv] reduce sim time for smoke test (Weicai Yang)
* [i2c, rtl] Lint Fixes (Igor Kouznetsov)
* [dv/stress_all_with_reset] Revert back IPs that uses apply_reset
  (Cindy Chen)
* [uart] Wire up integrity alert (Michael Schaffner)
* [gpio] Wire up bus integrity alert (Michael Schaffner)
* [i2c, dv] Fix csr_* and smoke test for I2C (Tung Hoang)
* [gpio/dv] add run-opt for gpio_tl_intg_err (Weicai Yang)
* [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy
  Chen)
* [reggen] Make spacing uniform and simplify comments in reg_top
  (Rupert Swarbrick)
* [spi_host] Wire up integrity alert (Michael Schaffner)
* [uart/dv] Fix unmapped test (Weicai Yang)
* [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner)
* [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops
  (Michael Schaffner)
* [i2c, rtl] Fixes to Lint Errors and Changes to Clock Stretching by
  Target (Igor Kouznetsov)
* [doc, testplans] Fix non-existent tests (Srikrishna Iyer)
* [i2c, rtl] Loopback test and other changes (Igor Kouznetsov)
* [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki)
* [rv_plic] fix Src width mismatch (Eunchan Kim)
* [prim] Break always_comb block to avoid apparent loop (Rupert
  Swarbrick)
* [fpv] update secded_gen (Cindy Chen)
* [dv/common] Improve coverage exclusion method (Cindy Chen)
* [dvsim] Testplanner refactor & covergroup support (Srikrishna Iyer)
* [otp_ctrl] Workaround for generated prim depending on generated prim
  (Michael Schaffner)
* [checklists] Update all checklists for consistency (Srikrishna Iyer)
* [prim_secded] Add C reference models for Hsiao encode (Greg
  Chadwick)
* [rtl/prim_async_fifo] Fix async fifo typo when depth <= 2 (Cindy
  Chen)
* [pads] - added AnalogIn1 pads for OTP supply (Arnon Sharlin)
* [dv/common] add ECC support to mem_bkdr_if (Udi Jonnalagadda)
* [prim_secded] Use _i/_o suffix for port names (Philipp Wagner)
* [prim_fifo_async] Style fixes (Philipp Wagner)
* [uart] Fix line continuation in DV code (Philipp Wagner)
* Remove non-ASCII characters from SV code and meson.build (Rupert
  Swarbrick)
* [ spi_host ] Remove cmd_len_q register to clean up DC logs (Martin
  Lueker-Boden)
* [fpv/spi_host] Fix undecleared variable issue (Cindy Chen)
* [ spi_device, spi_host, top_earlgrey ] Add SPI passthrough to
  spi_host (Martin Lueker-Boden)
* [uart,lint] Waive warning about unused field in uart reg2hw (Rupert
  Swarbrick)
* [ prim ] Suppress unneeded assertion when clearing prim_packer_fifo
  (Martin Lueker-Boden)
* [spi_host] Proper routing of sd_o in standard mode. (Martin Lueker-
  Boden)
* [all] Minor lint fixes (Timothy Chen)
* [regtool] Reformulate wr_err calculation to avoid long lines (Rupert
  Swarbrick)
* [prim_clock_div] Update waiver (Michael Schaffner)
* [prim] Make SECDED prim generation deterministic (Rupert Swarbrick)
* [prim_pad_attr/prim_flop_en] Add waiver files (Michael Schaffner)
* [spi_host] Minor lint fixes (Michael Schaffner)
* [prim_clock_div] Update waiver file (Michael Schaffner)
* [top] change prim_generic usage into prim (Timothy Chen)
* Add formatting changes from allow list (Rafal Kapuscik)
* [prim] Add generic and Xilinx-specific xor2 primitives (Pirmin
  Vogel)
* [prim] Add generic and Xilinx-specific enable-FF primitives (Pirmin
  Vogel)
* [ spi_host ] SPI_HOST Implementation (Martin Lueker-Boden)
* [pinmux/padring] Wire up the pad attribute WARL behavior modules
  (Michael Schaffner)
* [pad_wrapper] Extend the generic and Xilinx pad wrapper models
  (Michael Schaffner)
* [dv] Update scb for all blocks (Weicai Yang)
* [prim_arbiter,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [rv_plic,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [prim] Fix lint warnings, replace inline AscentLint waivers (Pirmin
  Vogel)
* [dv] Update `process_tl_access` args for all blocks (Weicai Yang)
* [formal] Clean up some formal warnings (Cindy Chen)
* [topgen] Rework pinmux datastructure and templatize tops (Michael
  Schaffner)
* [prim_fifo_async] Make async FIFO output zero when empty (Noah
  Moroze)
* [ci] Switch from a blacklist to a whitelist for executable files
  (Rupert Swarbrick)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

* vendor: Re-patch opentitan peripherals

* vendor: Fixes to opentitan SPI

* vendor: Add SV APB UART

* vendor: Patch SV APB UART

* occamy: Integrate 16550-compliant APB UART, regenerate PLIC

* vendor: Update patches

vendor: Update SPI patches

* occamy: Fix SoC control overlay RTL issue

* fpga: Replace Xilinx UART with internal one

* Remove the Xilinx UART from the Block Design
* Map internal UART to UART0 of VCU128
* Update device tree
* Update ZSBL

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
paulsc96 added a commit to pulp-platform/snitch_cluster that referenced this pull request Jul 11, 2023
…tch#207](#207s))

* vendor: Prevent recursive vendor patching of `register_interface`

* vendor: Update pulp_platform_register_interface to 73de8e5

Update code from upstream repository https://github.com/pulp-
platform/register_interface.git to revision
73de8e51b79f416350229b1d2420b2c527e002b8

* Release v0.3.1 (Manuel Eggimann)
* Update README (Manuel Eggimann)
* Align axi version in ips_list with Bender.yml (Manuel Eggimann)
* Release v0.3.0 (Manuel Eggimann)
* Bump AXI version (Manuel Eggimann)
* Update changelog (Manuel Eggimann)
* Rebased reggen patches on top of current master (Manuel Eggimann)
* Release v0.2.2 (Florian Zaruba)
* Bump axi version ([pulp-platform/snitch#12](#12s)) (Manuel Eggimann)
* ci: Also run on pull requests ([pulp-platform/snitch#11](#11s)) (Florian Zaruba)
* Add periph to register adapter ([pulp-platform/snitch#10](#10s)) (Michael Rogenmoser)
* Release v0.2.1 (Florian Zaruba)
* src_files.yml: Remove dropped pkg (bluew)
* Update axi and common_cells dependencies ([pulp-platform/snitch#9](#9s)) (Michael Rogenmoser)
* Add reggen register primitives to src_files.yml (Manuel Eggimann)
* Add ip_description for IPAppprox (Manuel Eggimann)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

python-requirements: Add yaml package

* vendor: Patch windowing bug in pulp_platform regtool

* vendor: Add regtool patch

* snitch_cluster: Regenerate peripheral registers with new generator

snitch_cluster: Remove non-existant DE connection in cluster peripherals

* occamy: Regenerate CLINT register interface

* occamy: Regenerate SoC registers

* vendor: Exclude unneeded files from opentitan vendor, remove UART

* vendor: Update lowrisc_opentitan to lowRISC/opentitan@726718a6d

Update code from upstream repository
https://github.com/lowRISC/opentitan.git to revision
726718a6de32aa047a4064e02e7b619699f054ed

* [dv/prim_esc] Fix prim_esc regression error (Cindy Chen)
* [spi_host,design] Properly handle TX "stall" and "flush" conditions
  (Martin Lueker-Boden)
* [sram_ctrl] Harden initialization counter (Michael Schaffner)
* [fpv/rv_plic] Fix assertion irq_id_o width (Cindy Chen)
* [prim] SRAM Async FIFO (Eunchan Kim)
* [prim_lfsr] Do not shadow |state| variable (Philipp Wagner)
* [prim] Add non-linear out option to prim_lfsr (Timothy Chen)
* [primgen] Instantiate tech libs in stable order (Philipp Wagner)
* [primgen] Actually find the Verible Python wrapper (Philipp Wagner)
* [dv/prim_esc] fix regression error (Cindy Chen)
* [dv/gpio] fix intr_test regression failure (Cindy Chen)
* [dv/common] Exclude assertion coverage from IP level testbench
  (Cindy Chen)
* [i2c, rtl] Update i2c.prj.hjson for D2 completion (Igor Kouznetsov)
* [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda)
* [sram_ctrl] Update docs (Michael Schaffner)
* [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner)
* [dv/gpio] Fix filter_stress test timeout (Cindy Chen)
* [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen)
* [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen)
* [dv/ips] Fix a few small items in gpio and hmac (Cindy Chen)
* [prim_xor2/lint] Add waiver for .* use in generated prim (Michael
  Schaffner)
* [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer)
* [util, reggen] Support standardized cdc handling for regfile
  (Timothy Chen)
* [spi_host/dv] updated checkout list to track doc and testplan status
  (Rasmus Madsen)
* [spi_host/dv/doc] Updated dv plan for spi host for V1 review (Rasmus
  Madsen)
* [spi_host/dv/doc] Updated spi_host testplan (Rasmus Madsen)
* [i2c, doc] Checklist Update for D2 Sign-off (Igor Kouznetsov)
* [rtl/prim_alert_sender] Allow ping_req to stay high without error
  (Cindy Chen)
* [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen)
* [prim_subreg_shadow] Make local parameter a localparam (Philipp
  Wagner)
* [prim_subreg] Make software access type an enum (Philipp Wagner)
* [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen)
* [edn] Add MaxLatency assertion (Eunchan Kim)
* [prim_subreg_shadow] Correct write data signal usage (Michael
  Schaffner)
* [prim_lfsr] Fix assertion issue occuring right after reset (Michael
  Schaffner)
* [memutil] Allow use without scrambled memories (Philipp Wagner)
* [prim_prince] Fix comment (Philipp Wagner)
* [memutil] Fix width mismatch (Philipp Wagner)
* [prim] Allow disabling SVAs ensuring REQ is held until ACK at run
  time (Pirmin Vogel)
* [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen)
* [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert
  Swarbrick)
* [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs
  (Michael Schaffner)
* [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug
  (Michael Schaffner)
* [primgen] Remove unused import (Philipp Wagner)
* [primgen] Add shebang (Philipp Wagner)
* [primgen] Make primgen "portable" again (Philipp Wagner)
* [rv_plic] rv_plic updates as part of rv_core_ibex templating
  (Timothy Chen)
* [ spi_host ] Fix Lint Errors (Martin Lueker-Boden)
* [fpv/rv_plic] Fix compile error with alert (Cindy Chen)
* [uart] Minor lint fix (Timothy Chen)
* [ spi_host ] Transition to D1 (Martin Lueker-Boden)
* [spi_host,doc] Update spi_host documentation (Martin Lueker-Boden)
* [pwm, dv] Fix fifo test for i2c host rtl (Tung Hoang)
* [dv/uart] Fix assertion (Weicai Yang)
* [doc/fpv] Unify the wording for IPs that verified in FPV (Cindy
  Chen)
* [reggen] Pair up clock and reset signals (Rupert Swarbrick)
* [integ alerts] Align description of integ alerts (Michael Schaffner)
* [tlul] Add some missing dependencies (Michael Schaffner)
* [rv_plic] Fix a bitwidth lint error (Michael Schaffner)
* [rv_plic] Wire up integ alert (Michael Schaffner)
* [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael
  Schaffner)
* [spi*/uart] Make sure integ alert is fatal (Michael Schaffner)
* [adc_ctrl] Various preparation steps for d2 (Timothy Chen)
* [dv/i2c] Fix alert clock/reset (Weicai Yang)
* [i2c, rtl] FIFO Depth Parameterization (Igor Kouznetsov)
* Revert "[prim] Do remove prim_esc.core from the dependencies"
  (Rupert Swarbrick)
* [prim] Remove dependency of prim:esc on a hardware block (Rupert
  Swarbrick)
* [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick)
* [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick)
* [dv] Add C++ memory scrambling model (Greg Chadwick)
* [prim] Do remove prim_esc.core from the dependencies (Michael
  Schaffner)
* [i2c, doc] Updated Description of Clock Stretching by Target (Igor
  Kouznetsov)
* [reggen] Generate a single we/re signal per register in reg_top
  (Rupert Swarbrick)
* [alert_handler] Implement reverse ping feature (Michael Schaffner)
* [prim_esc] Split the prims into their own core file (Michael
  Schaffner)
* [uart/dv] Fix regression failure (Weicai Yang)
* [dv/common] Stress_all_with_rand_reset apply reset concurrently
  (Cindy Chen)
* [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda)
* [i2c, rtl] Lint fixes (Igor Kouznetsov)
* [reggen] Simplify reg_top ports if there's exactly one window
  (Rupert Swarbrick)
* [prim_fifo_async] Fix a width calculation issue in case of Depth = 1
  (Michael Schaffner)
* [dv] Add automated alert_test to all IPs with new tl_int alert
  (Cindy Chen)
* [i2c] Wire up integrity alert (Michael Schaffner)
* [uart/dv] reduce sim time for smoke test (Weicai Yang)
* [i2c, rtl] Lint Fixes (Igor Kouznetsov)
* [dv/stress_all_with_reset] Revert back IPs that uses apply_reset
  (Cindy Chen)
* [uart] Wire up integrity alert (Michael Schaffner)
* [gpio] Wire up bus integrity alert (Michael Schaffner)
* [i2c, dv] Fix csr_* and smoke test for I2C (Tung Hoang)
* [gpio/dv] add run-opt for gpio_tl_intg_err (Weicai Yang)
* [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy
  Chen)
* [reggen] Make spacing uniform and simplify comments in reg_top
  (Rupert Swarbrick)
* [spi_host] Wire up integrity alert (Michael Schaffner)
* [uart/dv] Fix unmapped test (Weicai Yang)
* [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner)
* [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops
  (Michael Schaffner)
* [i2c, rtl] Fixes to Lint Errors and Changes to Clock Stretching by
  Target (Igor Kouznetsov)
* [doc, testplans] Fix non-existent tests (Srikrishna Iyer)
* [i2c, rtl] Loopback test and other changes (Igor Kouznetsov)
* [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki)
* [rv_plic] fix Src width mismatch (Eunchan Kim)
* [prim] Break always_comb block to avoid apparent loop (Rupert
  Swarbrick)
* [fpv] update secded_gen (Cindy Chen)
* [dv/common] Improve coverage exclusion method (Cindy Chen)
* [dvsim] Testplanner refactor & covergroup support (Srikrishna Iyer)
* [otp_ctrl] Workaround for generated prim depending on generated prim
  (Michael Schaffner)
* [checklists] Update all checklists for consistency (Srikrishna Iyer)
* [prim_secded] Add C reference models for Hsiao encode (Greg
  Chadwick)
* [rtl/prim_async_fifo] Fix async fifo typo when depth <= 2 (Cindy
  Chen)
* [pads] - added AnalogIn1 pads for OTP supply (Arnon Sharlin)
* [dv/common] add ECC support to mem_bkdr_if (Udi Jonnalagadda)
* [prim_secded] Use _i/_o suffix for port names (Philipp Wagner)
* [prim_fifo_async] Style fixes (Philipp Wagner)
* [uart] Fix line continuation in DV code (Philipp Wagner)
* Remove non-ASCII characters from SV code and meson.build (Rupert
  Swarbrick)
* [ spi_host ] Remove cmd_len_q register to clean up DC logs (Martin
  Lueker-Boden)
* [fpv/spi_host] Fix undecleared variable issue (Cindy Chen)
* [ spi_device, spi_host, top_earlgrey ] Add SPI passthrough to
  spi_host (Martin Lueker-Boden)
* [uart,lint] Waive warning about unused field in uart reg2hw (Rupert
  Swarbrick)
* [ prim ] Suppress unneeded assertion when clearing prim_packer_fifo
  (Martin Lueker-Boden)
* [spi_host] Proper routing of sd_o in standard mode. (Martin Lueker-
  Boden)
* [all] Minor lint fixes (Timothy Chen)
* [regtool] Reformulate wr_err calculation to avoid long lines (Rupert
  Swarbrick)
* [prim_clock_div] Update waiver (Michael Schaffner)
* [prim] Make SECDED prim generation deterministic (Rupert Swarbrick)
* [prim_pad_attr/prim_flop_en] Add waiver files (Michael Schaffner)
* [spi_host] Minor lint fixes (Michael Schaffner)
* [prim_clock_div] Update waiver file (Michael Schaffner)
* [top] change prim_generic usage into prim (Timothy Chen)
* Add formatting changes from allow list (Rafal Kapuscik)
* [prim] Add generic and Xilinx-specific xor2 primitives (Pirmin
  Vogel)
* [prim] Add generic and Xilinx-specific enable-FF primitives (Pirmin
  Vogel)
* [ spi_host ] SPI_HOST Implementation (Martin Lueker-Boden)
* [pinmux/padring] Wire up the pad attribute WARL behavior modules
  (Michael Schaffner)
* [pad_wrapper] Extend the generic and Xilinx pad wrapper models
  (Michael Schaffner)
* [dv] Update scb for all blocks (Weicai Yang)
* [prim_arbiter,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [rv_plic,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [prim] Fix lint warnings, replace inline AscentLint waivers (Pirmin
  Vogel)
* [dv] Update `process_tl_access` args for all blocks (Weicai Yang)
* [formal] Clean up some formal warnings (Cindy Chen)
* [topgen] Rework pinmux datastructure and templatize tops (Michael
  Schaffner)
* [prim_fifo_async] Make async FIFO output zero when empty (Noah
  Moroze)
* [ci] Switch from a blacklist to a whitelist for executable files
  (Rupert Swarbrick)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

* vendor: Re-patch opentitan peripherals

* vendor: Fixes to opentitan SPI

* vendor: Add SV APB UART

* vendor: Patch SV APB UART

* occamy: Integrate 16550-compliant APB UART, regenerate PLIC

* vendor: Update patches

vendor: Update SPI patches

* occamy: Fix SoC control overlay RTL issue

* fpga: Replace Xilinx UART with internal one

* Remove the Xilinx UART from the Block Design
* Map internal UART to UART0 of VCU128
* Update device tree
* Update ZSBL

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
paulsc96 added a commit to pulp-platform/snitch_cluster that referenced this pull request Jul 11, 2023
…ch#207)

* vendor: Prevent recursive vendor patching of `register_interface`

* vendor: Update pulp_platform_register_interface to 73de8e5

Update code from upstream repository https://github.com/pulp-
platform/register_interface.git to revision
73de8e51b79f416350229b1d2420b2c527e002b8

* Release v0.3.1 (Manuel Eggimann)
* Update README (Manuel Eggimann)
* Align axi version in ips_list with Bender.yml (Manuel Eggimann)
* Release v0.3.0 (Manuel Eggimann)
* Bump AXI version (Manuel Eggimann)
* Update changelog (Manuel Eggimann)
* Rebased reggen patches on top of current master (Manuel Eggimann)
* Release v0.2.2 (Florian Zaruba)
* Bump axi version (pulp-platform/snitch#12) (Manuel Eggimann)
* ci: Also run on pull requests (pulp-platform/snitch#11) (Florian Zaruba)
* Add periph to register adapter (pulp-platform/snitch#10) (Michael Rogenmoser)
* Release v0.2.1 (Florian Zaruba)
* src_files.yml: Remove dropped pkg (bluew)
* Update axi and common_cells dependencies (pulp-platform/snitch#9) (Michael Rogenmoser)
* Add reggen register primitives to src_files.yml (Manuel Eggimann)
* Add ip_description for IPAppprox (Manuel Eggimann)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

python-requirements: Add yaml package

* vendor: Patch windowing bug in pulp_platform regtool

* vendor: Add regtool patch

* snitch_cluster: Regenerate peripheral registers with new generator

snitch_cluster: Remove non-existant DE connection in cluster peripherals

* occamy: Regenerate CLINT register interface

* occamy: Regenerate SoC registers

* vendor: Exclude unneeded files from opentitan vendor, remove UART

* vendor: Update lowrisc_opentitan to lowRISC/opentitan@726718a6d

Update code from upstream repository
https://github.com/lowRISC/opentitan.git to revision
726718a6de32aa047a4064e02e7b619699f054ed

* [dv/prim_esc] Fix prim_esc regression error (Cindy Chen)
* [spi_host,design] Properly handle TX "stall" and "flush" conditions
  (Martin Lueker-Boden)
* [sram_ctrl] Harden initialization counter (Michael Schaffner)
* [fpv/rv_plic] Fix assertion irq_id_o width (Cindy Chen)
* [prim] SRAM Async FIFO (Eunchan Kim)
* [prim_lfsr] Do not shadow |state| variable (Philipp Wagner)
* [prim] Add non-linear out option to prim_lfsr (Timothy Chen)
* [primgen] Instantiate tech libs in stable order (Philipp Wagner)
* [primgen] Actually find the Verible Python wrapper (Philipp Wagner)
* [dv/prim_esc] fix regression error (Cindy Chen)
* [dv/gpio] fix intr_test regression failure (Cindy Chen)
* [dv/common] Exclude assertion coverage from IP level testbench
  (Cindy Chen)
* [i2c, rtl] Update i2c.prj.hjson for D2 completion (Igor Kouznetsov)
* [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda)
* [sram_ctrl] Update docs (Michael Schaffner)
* [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner)
* [dv/gpio] Fix filter_stress test timeout (Cindy Chen)
* [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen)
* [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen)
* [dv/ips] Fix a few small items in gpio and hmac (Cindy Chen)
* [prim_xor2/lint] Add waiver for .* use in generated prim (Michael
  Schaffner)
* [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer)
* [util, reggen] Support standardized cdc handling for regfile
  (Timothy Chen)
* [spi_host/dv] updated checkout list to track doc and testplan status
  (Rasmus Madsen)
* [spi_host/dv/doc] Updated dv plan for spi host for V1 review (Rasmus
  Madsen)
* [spi_host/dv/doc] Updated spi_host testplan (Rasmus Madsen)
* [i2c, doc] Checklist Update for D2 Sign-off (Igor Kouznetsov)
* [rtl/prim_alert_sender] Allow ping_req to stay high without error
  (Cindy Chen)
* [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen)
* [prim_subreg_shadow] Make local parameter a localparam (Philipp
  Wagner)
* [prim_subreg] Make software access type an enum (Philipp Wagner)
* [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen)
* [edn] Add MaxLatency assertion (Eunchan Kim)
* [prim_subreg_shadow] Correct write data signal usage (Michael
  Schaffner)
* [prim_lfsr] Fix assertion issue occuring right after reset (Michael
  Schaffner)
* [memutil] Allow use without scrambled memories (Philipp Wagner)
* [prim_prince] Fix comment (Philipp Wagner)
* [memutil] Fix width mismatch (Philipp Wagner)
* [prim] Allow disabling SVAs ensuring REQ is held until ACK at run
  time (Pirmin Vogel)
* [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen)
* [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert
  Swarbrick)
* [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs
  (Michael Schaffner)
* [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug
  (Michael Schaffner)
* [primgen] Remove unused import (Philipp Wagner)
* [primgen] Add shebang (Philipp Wagner)
* [primgen] Make primgen "portable" again (Philipp Wagner)
* [rv_plic] rv_plic updates as part of rv_core_ibex templating
  (Timothy Chen)
* [ spi_host ] Fix Lint Errors (Martin Lueker-Boden)
* [fpv/rv_plic] Fix compile error with alert (Cindy Chen)
* [uart] Minor lint fix (Timothy Chen)
* [ spi_host ] Transition to D1 (Martin Lueker-Boden)
* [spi_host,doc] Update spi_host documentation (Martin Lueker-Boden)
* [pwm, dv] Fix fifo test for i2c host rtl (Tung Hoang)
* [dv/uart] Fix assertion (Weicai Yang)
* [doc/fpv] Unify the wording for IPs that verified in FPV (Cindy
  Chen)
* [reggen] Pair up clock and reset signals (Rupert Swarbrick)
* [integ alerts] Align description of integ alerts (Michael Schaffner)
* [tlul] Add some missing dependencies (Michael Schaffner)
* [rv_plic] Fix a bitwidth lint error (Michael Schaffner)
* [rv_plic] Wire up integ alert (Michael Schaffner)
* [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael
  Schaffner)
* [spi*/uart] Make sure integ alert is fatal (Michael Schaffner)
* [adc_ctrl] Various preparation steps for d2 (Timothy Chen)
* [dv/i2c] Fix alert clock/reset (Weicai Yang)
* [i2c, rtl] FIFO Depth Parameterization (Igor Kouznetsov)
* Revert "[prim] Do remove prim_esc.core from the dependencies"
  (Rupert Swarbrick)
* [prim] Remove dependency of prim:esc on a hardware block (Rupert
  Swarbrick)
* [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick)
* [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick)
* [dv] Add C++ memory scrambling model (Greg Chadwick)
* [prim] Do remove prim_esc.core from the dependencies (Michael
  Schaffner)
* [i2c, doc] Updated Description of Clock Stretching by Target (Igor
  Kouznetsov)
* [reggen] Generate a single we/re signal per register in reg_top
  (Rupert Swarbrick)
* [alert_handler] Implement reverse ping feature (Michael Schaffner)
* [prim_esc] Split the prims into their own core file (Michael
  Schaffner)
* [uart/dv] Fix regression failure (Weicai Yang)
* [dv/common] Stress_all_with_rand_reset apply reset concurrently
  (Cindy Chen)
* [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda)
* [i2c, rtl] Lint fixes (Igor Kouznetsov)
* [reggen] Simplify reg_top ports if there's exactly one window
  (Rupert Swarbrick)
* [prim_fifo_async] Fix a width calculation issue in case of Depth = 1
  (Michael Schaffner)
* [dv] Add automated alert_test to all IPs with new tl_int alert
  (Cindy Chen)
* [i2c] Wire up integrity alert (Michael Schaffner)
* [uart/dv] reduce sim time for smoke test (Weicai Yang)
* [i2c, rtl] Lint Fixes (Igor Kouznetsov)
* [dv/stress_all_with_reset] Revert back IPs that uses apply_reset
  (Cindy Chen)
* [uart] Wire up integrity alert (Michael Schaffner)
* [gpio] Wire up bus integrity alert (Michael Schaffner)
* [i2c, dv] Fix csr_* and smoke test for I2C (Tung Hoang)
* [gpio/dv] add run-opt for gpio_tl_intg_err (Weicai Yang)
* [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy
  Chen)
* [reggen] Make spacing uniform and simplify comments in reg_top
  (Rupert Swarbrick)
* [spi_host] Wire up integrity alert (Michael Schaffner)
* [uart/dv] Fix unmapped test (Weicai Yang)
* [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner)
* [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops
  (Michael Schaffner)
* [i2c, rtl] Fixes to Lint Errors and Changes to Clock Stretching by
  Target (Igor Kouznetsov)
* [doc, testplans] Fix non-existent tests (Srikrishna Iyer)
* [i2c, rtl] Loopback test and other changes (Igor Kouznetsov)
* [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki)
* [rv_plic] fix Src width mismatch (Eunchan Kim)
* [prim] Break always_comb block to avoid apparent loop (Rupert
  Swarbrick)
* [fpv] update secded_gen (Cindy Chen)
* [dv/common] Improve coverage exclusion method (Cindy Chen)
* [dvsim] Testplanner refactor & covergroup support (Srikrishna Iyer)
* [otp_ctrl] Workaround for generated prim depending on generated prim
  (Michael Schaffner)
* [checklists] Update all checklists for consistency (Srikrishna Iyer)
* [prim_secded] Add C reference models for Hsiao encode (Greg
  Chadwick)
* [rtl/prim_async_fifo] Fix async fifo typo when depth <= 2 (Cindy
  Chen)
* [pads] - added AnalogIn1 pads for OTP supply (Arnon Sharlin)
* [dv/common] add ECC support to mem_bkdr_if (Udi Jonnalagadda)
* [prim_secded] Use _i/_o suffix for port names (Philipp Wagner)
* [prim_fifo_async] Style fixes (Philipp Wagner)
* [uart] Fix line continuation in DV code (Philipp Wagner)
* Remove non-ASCII characters from SV code and meson.build (Rupert
  Swarbrick)
* [ spi_host ] Remove cmd_len_q register to clean up DC logs (Martin
  Lueker-Boden)
* [fpv/spi_host] Fix undecleared variable issue (Cindy Chen)
* [ spi_device, spi_host, top_earlgrey ] Add SPI passthrough to
  spi_host (Martin Lueker-Boden)
* [uart,lint] Waive warning about unused field in uart reg2hw (Rupert
  Swarbrick)
* [ prim ] Suppress unneeded assertion when clearing prim_packer_fifo
  (Martin Lueker-Boden)
* [spi_host] Proper routing of sd_o in standard mode. (Martin Lueker-
  Boden)
* [all] Minor lint fixes (Timothy Chen)
* [regtool] Reformulate wr_err calculation to avoid long lines (Rupert
  Swarbrick)
* [prim_clock_div] Update waiver (Michael Schaffner)
* [prim] Make SECDED prim generation deterministic (Rupert Swarbrick)
* [prim_pad_attr/prim_flop_en] Add waiver files (Michael Schaffner)
* [spi_host] Minor lint fixes (Michael Schaffner)
* [prim_clock_div] Update waiver file (Michael Schaffner)
* [top] change prim_generic usage into prim (Timothy Chen)
* Add formatting changes from allow list (Rafal Kapuscik)
* [prim] Add generic and Xilinx-specific xor2 primitives (Pirmin
  Vogel)
* [prim] Add generic and Xilinx-specific enable-FF primitives (Pirmin
  Vogel)
* [ spi_host ] SPI_HOST Implementation (Martin Lueker-Boden)
* [pinmux/padring] Wire up the pad attribute WARL behavior modules
  (Michael Schaffner)
* [pad_wrapper] Extend the generic and Xilinx pad wrapper models
  (Michael Schaffner)
* [dv] Update scb for all blocks (Weicai Yang)
* [prim_arbiter,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [rv_plic,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [prim] Fix lint warnings, replace inline AscentLint waivers (Pirmin
  Vogel)
* [dv] Update `process_tl_access` args for all blocks (Weicai Yang)
* [formal] Clean up some formal warnings (Cindy Chen)
* [topgen] Rework pinmux datastructure and templatize tops (Michael
  Schaffner)
* [prim_fifo_async] Make async FIFO output zero when empty (Noah
  Moroze)
* [ci] Switch from a blacklist to a whitelist for executable files
  (Rupert Swarbrick)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

* vendor: Re-patch opentitan peripherals

* vendor: Fixes to opentitan SPI

* vendor: Add SV APB UART

* vendor: Patch SV APB UART

* occamy: Integrate 16550-compliant APB UART, regenerate PLIC

* vendor: Update patches

vendor: Update SPI patches

* occamy: Fix SoC control overlay RTL issue

* fpga: Replace Xilinx UART with internal one

* Remove the Xilinx UART from the Block Design
* Map internal UART to UART0 of VCU128
* Update device tree
* Update ZSBL

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
colluca pushed a commit to pulp-platform/snitch_cluster that referenced this pull request Jul 11, 2023
…ch#207)

* vendor: Prevent recursive vendor patching of `register_interface`

* vendor: Update pulp_platform_register_interface to 73de8e5

Update code from upstream repository https://github.com/pulp-
platform/register_interface.git to revision
73de8e51b79f416350229b1d2420b2c527e002b8

* Release v0.3.1 (Manuel Eggimann)
* Update README (Manuel Eggimann)
* Align axi version in ips_list with Bender.yml (Manuel Eggimann)
* Release v0.3.0 (Manuel Eggimann)
* Bump AXI version (Manuel Eggimann)
* Update changelog (Manuel Eggimann)
* Rebased reggen patches on top of current master (Manuel Eggimann)
* Release v0.2.2 (Florian Zaruba)
* Bump axi version (pulp-platform/snitch#12) (Manuel Eggimann)
* ci: Also run on pull requests (pulp-platform/snitch#11) (Florian Zaruba)
* Add periph to register adapter (pulp-platform/snitch#10) (Michael Rogenmoser)
* Release v0.2.1 (Florian Zaruba)
* src_files.yml: Remove dropped pkg (bluew)
* Update axi and common_cells dependencies (pulp-platform/snitch#9) (Michael Rogenmoser)
* Add reggen register primitives to src_files.yml (Manuel Eggimann)
* Add ip_description for IPAppprox (Manuel Eggimann)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

python-requirements: Add yaml package

* vendor: Patch windowing bug in pulp_platform regtool

* vendor: Add regtool patch

* snitch_cluster: Regenerate peripheral registers with new generator

snitch_cluster: Remove non-existant DE connection in cluster peripherals

* occamy: Regenerate CLINT register interface

* occamy: Regenerate SoC registers

* vendor: Exclude unneeded files from opentitan vendor, remove UART

* vendor: Update lowrisc_opentitan to lowRISC/opentitan@726718a6d

Update code from upstream repository
https://github.com/lowRISC/opentitan.git to revision
726718a6de32aa047a4064e02e7b619699f054ed

* [dv/prim_esc] Fix prim_esc regression error (Cindy Chen)
* [spi_host,design] Properly handle TX "stall" and "flush" conditions
  (Martin Lueker-Boden)
* [sram_ctrl] Harden initialization counter (Michael Schaffner)
* [fpv/rv_plic] Fix assertion irq_id_o width (Cindy Chen)
* [prim] SRAM Async FIFO (Eunchan Kim)
* [prim_lfsr] Do not shadow |state| variable (Philipp Wagner)
* [prim] Add non-linear out option to prim_lfsr (Timothy Chen)
* [primgen] Instantiate tech libs in stable order (Philipp Wagner)
* [primgen] Actually find the Verible Python wrapper (Philipp Wagner)
* [dv/prim_esc] fix regression error (Cindy Chen)
* [dv/gpio] fix intr_test regression failure (Cindy Chen)
* [dv/common] Exclude assertion coverage from IP level testbench
  (Cindy Chen)
* [i2c, rtl] Update i2c.prj.hjson for D2 completion (Igor Kouznetsov)
* [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda)
* [sram_ctrl] Update docs (Michael Schaffner)
* [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner)
* [dv/gpio] Fix filter_stress test timeout (Cindy Chen)
* [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen)
* [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen)
* [dv/ips] Fix a few small items in gpio and hmac (Cindy Chen)
* [prim_xor2/lint] Add waiver for .* use in generated prim (Michael
  Schaffner)
* [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer)
* [util, reggen] Support standardized cdc handling for regfile
  (Timothy Chen)
* [spi_host/dv] updated checkout list to track doc and testplan status
  (Rasmus Madsen)
* [spi_host/dv/doc] Updated dv plan for spi host for V1 review (Rasmus
  Madsen)
* [spi_host/dv/doc] Updated spi_host testplan (Rasmus Madsen)
* [i2c, doc] Checklist Update for D2 Sign-off (Igor Kouznetsov)
* [rtl/prim_alert_sender] Allow ping_req to stay high without error
  (Cindy Chen)
* [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen)
* [prim_subreg_shadow] Make local parameter a localparam (Philipp
  Wagner)
* [prim_subreg] Make software access type an enum (Philipp Wagner)
* [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen)
* [edn] Add MaxLatency assertion (Eunchan Kim)
* [prim_subreg_shadow] Correct write data signal usage (Michael
  Schaffner)
* [prim_lfsr] Fix assertion issue occuring right after reset (Michael
  Schaffner)
* [memutil] Allow use without scrambled memories (Philipp Wagner)
* [prim_prince] Fix comment (Philipp Wagner)
* [memutil] Fix width mismatch (Philipp Wagner)
* [prim] Allow disabling SVAs ensuring REQ is held until ACK at run
  time (Pirmin Vogel)
* [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen)
* [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert
  Swarbrick)
* [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs
  (Michael Schaffner)
* [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug
  (Michael Schaffner)
* [primgen] Remove unused import (Philipp Wagner)
* [primgen] Add shebang (Philipp Wagner)
* [primgen] Make primgen "portable" again (Philipp Wagner)
* [rv_plic] rv_plic updates as part of rv_core_ibex templating
  (Timothy Chen)
* [ spi_host ] Fix Lint Errors (Martin Lueker-Boden)
* [fpv/rv_plic] Fix compile error with alert (Cindy Chen)
* [uart] Minor lint fix (Timothy Chen)
* [ spi_host ] Transition to D1 (Martin Lueker-Boden)
* [spi_host,doc] Update spi_host documentation (Martin Lueker-Boden)
* [pwm, dv] Fix fifo test for i2c host rtl (Tung Hoang)
* [dv/uart] Fix assertion (Weicai Yang)
* [doc/fpv] Unify the wording for IPs that verified in FPV (Cindy
  Chen)
* [reggen] Pair up clock and reset signals (Rupert Swarbrick)
* [integ alerts] Align description of integ alerts (Michael Schaffner)
* [tlul] Add some missing dependencies (Michael Schaffner)
* [rv_plic] Fix a bitwidth lint error (Michael Schaffner)
* [rv_plic] Wire up integ alert (Michael Schaffner)
* [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael
  Schaffner)
* [spi*/uart] Make sure integ alert is fatal (Michael Schaffner)
* [adc_ctrl] Various preparation steps for d2 (Timothy Chen)
* [dv/i2c] Fix alert clock/reset (Weicai Yang)
* [i2c, rtl] FIFO Depth Parameterization (Igor Kouznetsov)
* Revert "[prim] Do remove prim_esc.core from the dependencies"
  (Rupert Swarbrick)
* [prim] Remove dependency of prim:esc on a hardware block (Rupert
  Swarbrick)
* [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick)
* [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick)
* [dv] Add C++ memory scrambling model (Greg Chadwick)
* [prim] Do remove prim_esc.core from the dependencies (Michael
  Schaffner)
* [i2c, doc] Updated Description of Clock Stretching by Target (Igor
  Kouznetsov)
* [reggen] Generate a single we/re signal per register in reg_top
  (Rupert Swarbrick)
* [alert_handler] Implement reverse ping feature (Michael Schaffner)
* [prim_esc] Split the prims into their own core file (Michael
  Schaffner)
* [uart/dv] Fix regression failure (Weicai Yang)
* [dv/common] Stress_all_with_rand_reset apply reset concurrently
  (Cindy Chen)
* [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda)
* [i2c, rtl] Lint fixes (Igor Kouznetsov)
* [reggen] Simplify reg_top ports if there's exactly one window
  (Rupert Swarbrick)
* [prim_fifo_async] Fix a width calculation issue in case of Depth = 1
  (Michael Schaffner)
* [dv] Add automated alert_test to all IPs with new tl_int alert
  (Cindy Chen)
* [i2c] Wire up integrity alert (Michael Schaffner)
* [uart/dv] reduce sim time for smoke test (Weicai Yang)
* [i2c, rtl] Lint Fixes (Igor Kouznetsov)
* [dv/stress_all_with_reset] Revert back IPs that uses apply_reset
  (Cindy Chen)
* [uart] Wire up integrity alert (Michael Schaffner)
* [gpio] Wire up bus integrity alert (Michael Schaffner)
* [i2c, dv] Fix csr_* and smoke test for I2C (Tung Hoang)
* [gpio/dv] add run-opt for gpio_tl_intg_err (Weicai Yang)
* [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy
  Chen)
* [reggen] Make spacing uniform and simplify comments in reg_top
  (Rupert Swarbrick)
* [spi_host] Wire up integrity alert (Michael Schaffner)
* [uart/dv] Fix unmapped test (Weicai Yang)
* [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner)
* [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops
  (Michael Schaffner)
* [i2c, rtl] Fixes to Lint Errors and Changes to Clock Stretching by
  Target (Igor Kouznetsov)
* [doc, testplans] Fix non-existent tests (Srikrishna Iyer)
* [i2c, rtl] Loopback test and other changes (Igor Kouznetsov)
* [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki)
* [rv_plic] fix Src width mismatch (Eunchan Kim)
* [prim] Break always_comb block to avoid apparent loop (Rupert
  Swarbrick)
* [fpv] update secded_gen (Cindy Chen)
* [dv/common] Improve coverage exclusion method (Cindy Chen)
* [dvsim] Testplanner refactor & covergroup support (Srikrishna Iyer)
* [otp_ctrl] Workaround for generated prim depending on generated prim
  (Michael Schaffner)
* [checklists] Update all checklists for consistency (Srikrishna Iyer)
* [prim_secded] Add C reference models for Hsiao encode (Greg
  Chadwick)
* [rtl/prim_async_fifo] Fix async fifo typo when depth <= 2 (Cindy
  Chen)
* [pads] - added AnalogIn1 pads for OTP supply (Arnon Sharlin)
* [dv/common] add ECC support to mem_bkdr_if (Udi Jonnalagadda)
* [prim_secded] Use _i/_o suffix for port names (Philipp Wagner)
* [prim_fifo_async] Style fixes (Philipp Wagner)
* [uart] Fix line continuation in DV code (Philipp Wagner)
* Remove non-ASCII characters from SV code and meson.build (Rupert
  Swarbrick)
* [ spi_host ] Remove cmd_len_q register to clean up DC logs (Martin
  Lueker-Boden)
* [fpv/spi_host] Fix undecleared variable issue (Cindy Chen)
* [ spi_device, spi_host, top_earlgrey ] Add SPI passthrough to
  spi_host (Martin Lueker-Boden)
* [uart,lint] Waive warning about unused field in uart reg2hw (Rupert
  Swarbrick)
* [ prim ] Suppress unneeded assertion when clearing prim_packer_fifo
  (Martin Lueker-Boden)
* [spi_host] Proper routing of sd_o in standard mode. (Martin Lueker-
  Boden)
* [all] Minor lint fixes (Timothy Chen)
* [regtool] Reformulate wr_err calculation to avoid long lines (Rupert
  Swarbrick)
* [prim_clock_div] Update waiver (Michael Schaffner)
* [prim] Make SECDED prim generation deterministic (Rupert Swarbrick)
* [prim_pad_attr/prim_flop_en] Add waiver files (Michael Schaffner)
* [spi_host] Minor lint fixes (Michael Schaffner)
* [prim_clock_div] Update waiver file (Michael Schaffner)
* [top] change prim_generic usage into prim (Timothy Chen)
* Add formatting changes from allow list (Rafal Kapuscik)
* [prim] Add generic and Xilinx-specific xor2 primitives (Pirmin
  Vogel)
* [prim] Add generic and Xilinx-specific enable-FF primitives (Pirmin
  Vogel)
* [ spi_host ] SPI_HOST Implementation (Martin Lueker-Boden)
* [pinmux/padring] Wire up the pad attribute WARL behavior modules
  (Michael Schaffner)
* [pad_wrapper] Extend the generic and Xilinx pad wrapper models
  (Michael Schaffner)
* [dv] Update scb for all blocks (Weicai Yang)
* [prim_arbiter,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [rv_plic,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [prim] Fix lint warnings, replace inline AscentLint waivers (Pirmin
  Vogel)
* [dv] Update `process_tl_access` args for all blocks (Weicai Yang)
* [formal] Clean up some formal warnings (Cindy Chen)
* [topgen] Rework pinmux datastructure and templatize tops (Michael
  Schaffner)
* [prim_fifo_async] Make async FIFO output zero when empty (Noah
  Moroze)
* [ci] Switch from a blacklist to a whitelist for executable files
  (Rupert Swarbrick)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

* vendor: Re-patch opentitan peripherals

* vendor: Fixes to opentitan SPI

* vendor: Add SV APB UART

* vendor: Patch SV APB UART

* occamy: Integrate 16550-compliant APB UART, regenerate PLIC

* vendor: Update patches

vendor: Update SPI patches

* occamy: Fix SoC control overlay RTL issue

* fpga: Replace Xilinx UART with internal one

* Remove the Xilinx UART from the Block Design
* Map internal UART to UART0 of VCU128
* Update device tree
* Update ZSBL

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
paulsc96 added a commit to pulp-platform/snitch_cluster that referenced this pull request Jul 11, 2023
…ch#207)

* vendor: Prevent recursive vendor patching of `register_interface`

* vendor: Update pulp_platform_register_interface to 73de8e5

Update code from upstream repository https://github.com/pulp-
platform/register_interface.git to revision
73de8e51b79f416350229b1d2420b2c527e002b8

* Release v0.3.1 (Manuel Eggimann)
* Update README (Manuel Eggimann)
* Align axi version in ips_list with Bender.yml (Manuel Eggimann)
* Release v0.3.0 (Manuel Eggimann)
* Bump AXI version (Manuel Eggimann)
* Update changelog (Manuel Eggimann)
* Rebased reggen patches on top of current master (Manuel Eggimann)
* Release v0.2.2 (Florian Zaruba)
* Bump axi version (pulp-platform/snitch#12) (Manuel Eggimann)
* ci: Also run on pull requests (pulp-platform/snitch#11) (Florian Zaruba)
* Add periph to register adapter (pulp-platform/snitch#10) (Michael Rogenmoser)
* Release v0.2.1 (Florian Zaruba)
* src_files.yml: Remove dropped pkg (bluew)
* Update axi and common_cells dependencies (pulp-platform/snitch#9) (Michael Rogenmoser)
* Add reggen register primitives to src_files.yml (Manuel Eggimann)
* Add ip_description for IPAppprox (Manuel Eggimann)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

python-requirements: Add yaml package

* vendor: Patch windowing bug in pulp_platform regtool

* vendor: Add regtool patch

* snitch_cluster: Regenerate peripheral registers with new generator

snitch_cluster: Remove non-existant DE connection in cluster peripherals

* occamy: Regenerate CLINT register interface

* occamy: Regenerate SoC registers

* vendor: Exclude unneeded files from opentitan vendor, remove UART

* vendor: Update lowrisc_opentitan to lowRISC/opentitan@726718a6d

Update code from upstream repository
https://github.com/lowRISC/opentitan.git to revision
726718a6de32aa047a4064e02e7b619699f054ed

* [dv/prim_esc] Fix prim_esc regression error (Cindy Chen)
* [spi_host,design] Properly handle TX "stall" and "flush" conditions
  (Martin Lueker-Boden)
* [sram_ctrl] Harden initialization counter (Michael Schaffner)
* [fpv/rv_plic] Fix assertion irq_id_o width (Cindy Chen)
* [prim] SRAM Async FIFO (Eunchan Kim)
* [prim_lfsr] Do not shadow |state| variable (Philipp Wagner)
* [prim] Add non-linear out option to prim_lfsr (Timothy Chen)
* [primgen] Instantiate tech libs in stable order (Philipp Wagner)
* [primgen] Actually find the Verible Python wrapper (Philipp Wagner)
* [dv/prim_esc] fix regression error (Cindy Chen)
* [dv/gpio] fix intr_test regression failure (Cindy Chen)
* [dv/common] Exclude assertion coverage from IP level testbench
  (Cindy Chen)
* [i2c, rtl] Update i2c.prj.hjson for D2 completion (Igor Kouznetsov)
* [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda)
* [sram_ctrl] Update docs (Michael Schaffner)
* [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner)
* [dv/gpio] Fix filter_stress test timeout (Cindy Chen)
* [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen)
* [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen)
* [dv/ips] Fix a few small items in gpio and hmac (Cindy Chen)
* [prim_xor2/lint] Add waiver for .* use in generated prim (Michael
  Schaffner)
* [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer)
* [util, reggen] Support standardized cdc handling for regfile
  (Timothy Chen)
* [spi_host/dv] updated checkout list to track doc and testplan status
  (Rasmus Madsen)
* [spi_host/dv/doc] Updated dv plan for spi host for V1 review (Rasmus
  Madsen)
* [spi_host/dv/doc] Updated spi_host testplan (Rasmus Madsen)
* [i2c, doc] Checklist Update for D2 Sign-off (Igor Kouznetsov)
* [rtl/prim_alert_sender] Allow ping_req to stay high without error
  (Cindy Chen)
* [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen)
* [prim_subreg_shadow] Make local parameter a localparam (Philipp
  Wagner)
* [prim_subreg] Make software access type an enum (Philipp Wagner)
* [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen)
* [edn] Add MaxLatency assertion (Eunchan Kim)
* [prim_subreg_shadow] Correct write data signal usage (Michael
  Schaffner)
* [prim_lfsr] Fix assertion issue occuring right after reset (Michael
  Schaffner)
* [memutil] Allow use without scrambled memories (Philipp Wagner)
* [prim_prince] Fix comment (Philipp Wagner)
* [memutil] Fix width mismatch (Philipp Wagner)
* [prim] Allow disabling SVAs ensuring REQ is held until ACK at run
  time (Pirmin Vogel)
* [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen)
* [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert
  Swarbrick)
* [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs
  (Michael Schaffner)
* [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug
  (Michael Schaffner)
* [primgen] Remove unused import (Philipp Wagner)
* [primgen] Add shebang (Philipp Wagner)
* [primgen] Make primgen "portable" again (Philipp Wagner)
* [rv_plic] rv_plic updates as part of rv_core_ibex templating
  (Timothy Chen)
* [ spi_host ] Fix Lint Errors (Martin Lueker-Boden)
* [fpv/rv_plic] Fix compile error with alert (Cindy Chen)
* [uart] Minor lint fix (Timothy Chen)
* [ spi_host ] Transition to D1 (Martin Lueker-Boden)
* [spi_host,doc] Update spi_host documentation (Martin Lueker-Boden)
* [pwm, dv] Fix fifo test for i2c host rtl (Tung Hoang)
* [dv/uart] Fix assertion (Weicai Yang)
* [doc/fpv] Unify the wording for IPs that verified in FPV (Cindy
  Chen)
* [reggen] Pair up clock and reset signals (Rupert Swarbrick)
* [integ alerts] Align description of integ alerts (Michael Schaffner)
* [tlul] Add some missing dependencies (Michael Schaffner)
* [rv_plic] Fix a bitwidth lint error (Michael Schaffner)
* [rv_plic] Wire up integ alert (Michael Schaffner)
* [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael
  Schaffner)
* [spi*/uart] Make sure integ alert is fatal (Michael Schaffner)
* [adc_ctrl] Various preparation steps for d2 (Timothy Chen)
* [dv/i2c] Fix alert clock/reset (Weicai Yang)
* [i2c, rtl] FIFO Depth Parameterization (Igor Kouznetsov)
* Revert "[prim] Do remove prim_esc.core from the dependencies"
  (Rupert Swarbrick)
* [prim] Remove dependency of prim:esc on a hardware block (Rupert
  Swarbrick)
* [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick)
* [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick)
* [dv] Add C++ memory scrambling model (Greg Chadwick)
* [prim] Do remove prim_esc.core from the dependencies (Michael
  Schaffner)
* [i2c, doc] Updated Description of Clock Stretching by Target (Igor
  Kouznetsov)
* [reggen] Generate a single we/re signal per register in reg_top
  (Rupert Swarbrick)
* [alert_handler] Implement reverse ping feature (Michael Schaffner)
* [prim_esc] Split the prims into their own core file (Michael
  Schaffner)
* [uart/dv] Fix regression failure (Weicai Yang)
* [dv/common] Stress_all_with_rand_reset apply reset concurrently
  (Cindy Chen)
* [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda)
* [i2c, rtl] Lint fixes (Igor Kouznetsov)
* [reggen] Simplify reg_top ports if there's exactly one window
  (Rupert Swarbrick)
* [prim_fifo_async] Fix a width calculation issue in case of Depth = 1
  (Michael Schaffner)
* [dv] Add automated alert_test to all IPs with new tl_int alert
  (Cindy Chen)
* [i2c] Wire up integrity alert (Michael Schaffner)
* [uart/dv] reduce sim time for smoke test (Weicai Yang)
* [i2c, rtl] Lint Fixes (Igor Kouznetsov)
* [dv/stress_all_with_reset] Revert back IPs that uses apply_reset
  (Cindy Chen)
* [uart] Wire up integrity alert (Michael Schaffner)
* [gpio] Wire up bus integrity alert (Michael Schaffner)
* [i2c, dv] Fix csr_* and smoke test for I2C (Tung Hoang)
* [gpio/dv] add run-opt for gpio_tl_intg_err (Weicai Yang)
* [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy
  Chen)
* [reggen] Make spacing uniform and simplify comments in reg_top
  (Rupert Swarbrick)
* [spi_host] Wire up integrity alert (Michael Schaffner)
* [uart/dv] Fix unmapped test (Weicai Yang)
* [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner)
* [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops
  (Michael Schaffner)
* [i2c, rtl] Fixes to Lint Errors and Changes to Clock Stretching by
  Target (Igor Kouznetsov)
* [doc, testplans] Fix non-existent tests (Srikrishna Iyer)
* [i2c, rtl] Loopback test and other changes (Igor Kouznetsov)
* [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki)
* [rv_plic] fix Src width mismatch (Eunchan Kim)
* [prim] Break always_comb block to avoid apparent loop (Rupert
  Swarbrick)
* [fpv] update secded_gen (Cindy Chen)
* [dv/common] Improve coverage exclusion method (Cindy Chen)
* [dvsim] Testplanner refactor & covergroup support (Srikrishna Iyer)
* [otp_ctrl] Workaround for generated prim depending on generated prim
  (Michael Schaffner)
* [checklists] Update all checklists for consistency (Srikrishna Iyer)
* [prim_secded] Add C reference models for Hsiao encode (Greg
  Chadwick)
* [rtl/prim_async_fifo] Fix async fifo typo when depth <= 2 (Cindy
  Chen)
* [pads] - added AnalogIn1 pads for OTP supply (Arnon Sharlin)
* [dv/common] add ECC support to mem_bkdr_if (Udi Jonnalagadda)
* [prim_secded] Use _i/_o suffix for port names (Philipp Wagner)
* [prim_fifo_async] Style fixes (Philipp Wagner)
* [uart] Fix line continuation in DV code (Philipp Wagner)
* Remove non-ASCII characters from SV code and meson.build (Rupert
  Swarbrick)
* [ spi_host ] Remove cmd_len_q register to clean up DC logs (Martin
  Lueker-Boden)
* [fpv/spi_host] Fix undecleared variable issue (Cindy Chen)
* [ spi_device, spi_host, top_earlgrey ] Add SPI passthrough to
  spi_host (Martin Lueker-Boden)
* [uart,lint] Waive warning about unused field in uart reg2hw (Rupert
  Swarbrick)
* [ prim ] Suppress unneeded assertion when clearing prim_packer_fifo
  (Martin Lueker-Boden)
* [spi_host] Proper routing of sd_o in standard mode. (Martin Lueker-
  Boden)
* [all] Minor lint fixes (Timothy Chen)
* [regtool] Reformulate wr_err calculation to avoid long lines (Rupert
  Swarbrick)
* [prim_clock_div] Update waiver (Michael Schaffner)
* [prim] Make SECDED prim generation deterministic (Rupert Swarbrick)
* [prim_pad_attr/prim_flop_en] Add waiver files (Michael Schaffner)
* [spi_host] Minor lint fixes (Michael Schaffner)
* [prim_clock_div] Update waiver file (Michael Schaffner)
* [top] change prim_generic usage into prim (Timothy Chen)
* Add formatting changes from allow list (Rafal Kapuscik)
* [prim] Add generic and Xilinx-specific xor2 primitives (Pirmin
  Vogel)
* [prim] Add generic and Xilinx-specific enable-FF primitives (Pirmin
  Vogel)
* [ spi_host ] SPI_HOST Implementation (Martin Lueker-Boden)
* [pinmux/padring] Wire up the pad attribute WARL behavior modules
  (Michael Schaffner)
* [pad_wrapper] Extend the generic and Xilinx pad wrapper models
  (Michael Schaffner)
* [dv] Update scb for all blocks (Weicai Yang)
* [prim_arbiter,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [rv_plic,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [prim] Fix lint warnings, replace inline AscentLint waivers (Pirmin
  Vogel)
* [dv] Update `process_tl_access` args for all blocks (Weicai Yang)
* [formal] Clean up some formal warnings (Cindy Chen)
* [topgen] Rework pinmux datastructure and templatize tops (Michael
  Schaffner)
* [prim_fifo_async] Make async FIFO output zero when empty (Noah
  Moroze)
* [ci] Switch from a blacklist to a whitelist for executable files
  (Rupert Swarbrick)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

* vendor: Re-patch opentitan peripherals

* vendor: Fixes to opentitan SPI

* vendor: Add SV APB UART

* vendor: Patch SV APB UART

* occamy: Integrate 16550-compliant APB UART, regenerate PLIC

* vendor: Update patches

vendor: Update SPI patches

* occamy: Fix SoC control overlay RTL issue

* fpga: Replace Xilinx UART with internal one

* Remove the Xilinx UART from the Block Design
* Map internal UART to UART0 of VCU128
* Update device tree
* Update ZSBL

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
paulsc96 added a commit to pulp-platform/snitch_cluster that referenced this pull request Jul 11, 2023
…ch#207)

* vendor: Prevent recursive vendor patching of `register_interface`

* vendor: Update pulp_platform_register_interface to 73de8e5

Update code from upstream repository https://github.com/pulp-
platform/register_interface.git to revision
73de8e51b79f416350229b1d2420b2c527e002b8

* Release v0.3.1 (Manuel Eggimann)
* Update README (Manuel Eggimann)
* Align axi version in ips_list with Bender.yml (Manuel Eggimann)
* Release v0.3.0 (Manuel Eggimann)
* Bump AXI version (Manuel Eggimann)
* Update changelog (Manuel Eggimann)
* Rebased reggen patches on top of current master (Manuel Eggimann)
* Release v0.2.2 (Florian Zaruba)
* Bump axi version (pulp-platform/snitch#12) (Manuel Eggimann)
* ci: Also run on pull requests (pulp-platform/snitch#11) (Florian Zaruba)
* Add periph to register adapter (pulp-platform/snitch#10) (Michael Rogenmoser)
* Release v0.2.1 (Florian Zaruba)
* src_files.yml: Remove dropped pkg (bluew)
* Update axi and common_cells dependencies (pulp-platform/snitch#9) (Michael Rogenmoser)
* Add reggen register primitives to src_files.yml (Manuel Eggimann)
* Add ip_description for IPAppprox (Manuel Eggimann)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

python-requirements: Add yaml package

* vendor: Patch windowing bug in pulp_platform regtool

* vendor: Add regtool patch

* snitch_cluster: Regenerate peripheral registers with new generator

snitch_cluster: Remove non-existant DE connection in cluster peripherals

* occamy: Regenerate CLINT register interface

* occamy: Regenerate SoC registers

* vendor: Exclude unneeded files from opentitan vendor, remove UART

* vendor: Update lowrisc_opentitan to lowRISC/opentitan@726718a6d

Update code from upstream repository
https://github.com/lowRISC/opentitan.git to revision
726718a6de32aa047a4064e02e7b619699f054ed

* [dv/prim_esc] Fix prim_esc regression error (Cindy Chen)
* [spi_host,design] Properly handle TX "stall" and "flush" conditions
  (Martin Lueker-Boden)
* [sram_ctrl] Harden initialization counter (Michael Schaffner)
* [fpv/rv_plic] Fix assertion irq_id_o width (Cindy Chen)
* [prim] SRAM Async FIFO (Eunchan Kim)
* [prim_lfsr] Do not shadow |state| variable (Philipp Wagner)
* [prim] Add non-linear out option to prim_lfsr (Timothy Chen)
* [primgen] Instantiate tech libs in stable order (Philipp Wagner)
* [primgen] Actually find the Verible Python wrapper (Philipp Wagner)
* [dv/prim_esc] fix regression error (Cindy Chen)
* [dv/gpio] fix intr_test regression failure (Cindy Chen)
* [dv/common] Exclude assertion coverage from IP level testbench
  (Cindy Chen)
* [i2c, rtl] Update i2c.prj.hjson for D2 completion (Igor Kouznetsov)
* [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda)
* [sram_ctrl] Update docs (Michael Schaffner)
* [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner)
* [dv/gpio] Fix filter_stress test timeout (Cindy Chen)
* [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen)
* [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen)
* [dv/ips] Fix a few small items in gpio and hmac (Cindy Chen)
* [prim_xor2/lint] Add waiver for .* use in generated prim (Michael
  Schaffner)
* [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer)
* [util, reggen] Support standardized cdc handling for regfile
  (Timothy Chen)
* [spi_host/dv] updated checkout list to track doc and testplan status
  (Rasmus Madsen)
* [spi_host/dv/doc] Updated dv plan for spi host for V1 review (Rasmus
  Madsen)
* [spi_host/dv/doc] Updated spi_host testplan (Rasmus Madsen)
* [i2c, doc] Checklist Update for D2 Sign-off (Igor Kouznetsov)
* [rtl/prim_alert_sender] Allow ping_req to stay high without error
  (Cindy Chen)
* [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen)
* [prim_subreg_shadow] Make local parameter a localparam (Philipp
  Wagner)
* [prim_subreg] Make software access type an enum (Philipp Wagner)
* [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen)
* [edn] Add MaxLatency assertion (Eunchan Kim)
* [prim_subreg_shadow] Correct write data signal usage (Michael
  Schaffner)
* [prim_lfsr] Fix assertion issue occuring right after reset (Michael
  Schaffner)
* [memutil] Allow use without scrambled memories (Philipp Wagner)
* [prim_prince] Fix comment (Philipp Wagner)
* [memutil] Fix width mismatch (Philipp Wagner)
* [prim] Allow disabling SVAs ensuring REQ is held until ACK at run
  time (Pirmin Vogel)
* [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen)
* [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert
  Swarbrick)
* [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs
  (Michael Schaffner)
* [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug
  (Michael Schaffner)
* [primgen] Remove unused import (Philipp Wagner)
* [primgen] Add shebang (Philipp Wagner)
* [primgen] Make primgen "portable" again (Philipp Wagner)
* [rv_plic] rv_plic updates as part of rv_core_ibex templating
  (Timothy Chen)
* [ spi_host ] Fix Lint Errors (Martin Lueker-Boden)
* [fpv/rv_plic] Fix compile error with alert (Cindy Chen)
* [uart] Minor lint fix (Timothy Chen)
* [ spi_host ] Transition to D1 (Martin Lueker-Boden)
* [spi_host,doc] Update spi_host documentation (Martin Lueker-Boden)
* [pwm, dv] Fix fifo test for i2c host rtl (Tung Hoang)
* [dv/uart] Fix assertion (Weicai Yang)
* [doc/fpv] Unify the wording for IPs that verified in FPV (Cindy
  Chen)
* [reggen] Pair up clock and reset signals (Rupert Swarbrick)
* [integ alerts] Align description of integ alerts (Michael Schaffner)
* [tlul] Add some missing dependencies (Michael Schaffner)
* [rv_plic] Fix a bitwidth lint error (Michael Schaffner)
* [rv_plic] Wire up integ alert (Michael Schaffner)
* [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael
  Schaffner)
* [spi*/uart] Make sure integ alert is fatal (Michael Schaffner)
* [adc_ctrl] Various preparation steps for d2 (Timothy Chen)
* [dv/i2c] Fix alert clock/reset (Weicai Yang)
* [i2c, rtl] FIFO Depth Parameterization (Igor Kouznetsov)
* Revert "[prim] Do remove prim_esc.core from the dependencies"
  (Rupert Swarbrick)
* [prim] Remove dependency of prim:esc on a hardware block (Rupert
  Swarbrick)
* [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick)
* [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick)
* [dv] Add C++ memory scrambling model (Greg Chadwick)
* [prim] Do remove prim_esc.core from the dependencies (Michael
  Schaffner)
* [i2c, doc] Updated Description of Clock Stretching by Target (Igor
  Kouznetsov)
* [reggen] Generate a single we/re signal per register in reg_top
  (Rupert Swarbrick)
* [alert_handler] Implement reverse ping feature (Michael Schaffner)
* [prim_esc] Split the prims into their own core file (Michael
  Schaffner)
* [uart/dv] Fix regression failure (Weicai Yang)
* [dv/common] Stress_all_with_rand_reset apply reset concurrently
  (Cindy Chen)
* [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda)
* [i2c, rtl] Lint fixes (Igor Kouznetsov)
* [reggen] Simplify reg_top ports if there's exactly one window
  (Rupert Swarbrick)
* [prim_fifo_async] Fix a width calculation issue in case of Depth = 1
  (Michael Schaffner)
* [dv] Add automated alert_test to all IPs with new tl_int alert
  (Cindy Chen)
* [i2c] Wire up integrity alert (Michael Schaffner)
* [uart/dv] reduce sim time for smoke test (Weicai Yang)
* [i2c, rtl] Lint Fixes (Igor Kouznetsov)
* [dv/stress_all_with_reset] Revert back IPs that uses apply_reset
  (Cindy Chen)
* [uart] Wire up integrity alert (Michael Schaffner)
* [gpio] Wire up bus integrity alert (Michael Schaffner)
* [i2c, dv] Fix csr_* and smoke test for I2C (Tung Hoang)
* [gpio/dv] add run-opt for gpio_tl_intg_err (Weicai Yang)
* [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy
  Chen)
* [reggen] Make spacing uniform and simplify comments in reg_top
  (Rupert Swarbrick)
* [spi_host] Wire up integrity alert (Michael Schaffner)
* [uart/dv] Fix unmapped test (Weicai Yang)
* [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner)
* [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops
  (Michael Schaffner)
* [i2c, rtl] Fixes to Lint Errors and Changes to Clock Stretching by
  Target (Igor Kouznetsov)
* [doc, testplans] Fix non-existent tests (Srikrishna Iyer)
* [i2c, rtl] Loopback test and other changes (Igor Kouznetsov)
* [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki)
* [rv_plic] fix Src width mismatch (Eunchan Kim)
* [prim] Break always_comb block to avoid apparent loop (Rupert
  Swarbrick)
* [fpv] update secded_gen (Cindy Chen)
* [dv/common] Improve coverage exclusion method (Cindy Chen)
* [dvsim] Testplanner refactor & covergroup support (Srikrishna Iyer)
* [otp_ctrl] Workaround for generated prim depending on generated prim
  (Michael Schaffner)
* [checklists] Update all checklists for consistency (Srikrishna Iyer)
* [prim_secded] Add C reference models for Hsiao encode (Greg
  Chadwick)
* [rtl/prim_async_fifo] Fix async fifo typo when depth <= 2 (Cindy
  Chen)
* [pads] - added AnalogIn1 pads for OTP supply (Arnon Sharlin)
* [dv/common] add ECC support to mem_bkdr_if (Udi Jonnalagadda)
* [prim_secded] Use _i/_o suffix for port names (Philipp Wagner)
* [prim_fifo_async] Style fixes (Philipp Wagner)
* [uart] Fix line continuation in DV code (Philipp Wagner)
* Remove non-ASCII characters from SV code and meson.build (Rupert
  Swarbrick)
* [ spi_host ] Remove cmd_len_q register to clean up DC logs (Martin
  Lueker-Boden)
* [fpv/spi_host] Fix undecleared variable issue (Cindy Chen)
* [ spi_device, spi_host, top_earlgrey ] Add SPI passthrough to
  spi_host (Martin Lueker-Boden)
* [uart,lint] Waive warning about unused field in uart reg2hw (Rupert
  Swarbrick)
* [ prim ] Suppress unneeded assertion when clearing prim_packer_fifo
  (Martin Lueker-Boden)
* [spi_host] Proper routing of sd_o in standard mode. (Martin Lueker-
  Boden)
* [all] Minor lint fixes (Timothy Chen)
* [regtool] Reformulate wr_err calculation to avoid long lines (Rupert
  Swarbrick)
* [prim_clock_div] Update waiver (Michael Schaffner)
* [prim] Make SECDED prim generation deterministic (Rupert Swarbrick)
* [prim_pad_attr/prim_flop_en] Add waiver files (Michael Schaffner)
* [spi_host] Minor lint fixes (Michael Schaffner)
* [prim_clock_div] Update waiver file (Michael Schaffner)
* [top] change prim_generic usage into prim (Timothy Chen)
* Add formatting changes from allow list (Rafal Kapuscik)
* [prim] Add generic and Xilinx-specific xor2 primitives (Pirmin
  Vogel)
* [prim] Add generic and Xilinx-specific enable-FF primitives (Pirmin
  Vogel)
* [ spi_host ] SPI_HOST Implementation (Martin Lueker-Boden)
* [pinmux/padring] Wire up the pad attribute WARL behavior modules
  (Michael Schaffner)
* [pad_wrapper] Extend the generic and Xilinx pad wrapper models
  (Michael Schaffner)
* [dv] Update scb for all blocks (Weicai Yang)
* [prim_arbiter,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [rv_plic,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [prim] Fix lint warnings, replace inline AscentLint waivers (Pirmin
  Vogel)
* [dv] Update `process_tl_access` args for all blocks (Weicai Yang)
* [formal] Clean up some formal warnings (Cindy Chen)
* [topgen] Rework pinmux datastructure and templatize tops (Michael
  Schaffner)
* [prim_fifo_async] Make async FIFO output zero when empty (Noah
  Moroze)
* [ci] Switch from a blacklist to a whitelist for executable files
  (Rupert Swarbrick)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

* vendor: Re-patch opentitan peripherals

* vendor: Fixes to opentitan SPI

* vendor: Add SV APB UART

* vendor: Patch SV APB UART

* occamy: Integrate 16550-compliant APB UART, regenerate PLIC

* vendor: Update patches

vendor: Update SPI patches

* occamy: Fix SoC control overlay RTL issue

* fpga: Replace Xilinx UART with internal one

* Remove the Xilinx UART from the Block Design
* Map internal UART to UART0 of VCU128
* Update device tree
* Update ZSBL

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
colluca pushed a commit to pulp-platform/occamy that referenced this pull request Aug 19, 2023
…ch#207)

* vendor: Prevent recursive vendor patching of `register_interface`

* vendor: Update pulp_platform_register_interface to 73de8e5

Update code from upstream repository https://github.com/pulp-
platform/register_interface.git to revision
73de8e51b79f416350229b1d2420b2c527e002b8

* Release v0.3.1 (Manuel Eggimann)
* Update README (Manuel Eggimann)
* Align axi version in ips_list with Bender.yml (Manuel Eggimann)
* Release v0.3.0 (Manuel Eggimann)
* Bump AXI version (Manuel Eggimann)
* Update changelog (Manuel Eggimann)
* Rebased reggen patches on top of current master (Manuel Eggimann)
* Release v0.2.2 (Florian Zaruba)
* Bump axi version (pulp-platform/snitch#12) (Manuel Eggimann)
* ci: Also run on pull requests (pulp-platform/snitch#11) (Florian Zaruba)
* Add periph to register adapter (pulp-platform/snitch#10) (Michael Rogenmoser)
* Release v0.2.1 (Florian Zaruba)
* src_files.yml: Remove dropped pkg (bluew)
* Update axi and common_cells dependencies (pulp-platform/snitch#9) (Michael Rogenmoser)
* Add reggen register primitives to src_files.yml (Manuel Eggimann)
* Add ip_description for IPAppprox (Manuel Eggimann)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

python-requirements: Add yaml package

* vendor: Patch windowing bug in pulp_platform regtool

* vendor: Add regtool patch

* snitch_cluster: Regenerate peripheral registers with new generator

snitch_cluster: Remove non-existant DE connection in cluster peripherals

* occamy: Regenerate CLINT register interface

* occamy: Regenerate SoC registers

* vendor: Exclude unneeded files from opentitan vendor, remove UART

* vendor: Update lowrisc_opentitan to lowRISC/opentitan@726718a6d

Update code from upstream repository
https://github.com/lowRISC/opentitan.git to revision
726718a6de32aa047a4064e02e7b619699f054ed

* [dv/prim_esc] Fix prim_esc regression error (Cindy Chen)
* [spi_host,design] Properly handle TX "stall" and "flush" conditions
  (Martin Lueker-Boden)
* [sram_ctrl] Harden initialization counter (Michael Schaffner)
* [fpv/rv_plic] Fix assertion irq_id_o width (Cindy Chen)
* [prim] SRAM Async FIFO (Eunchan Kim)
* [prim_lfsr] Do not shadow |state| variable (Philipp Wagner)
* [prim] Add non-linear out option to prim_lfsr (Timothy Chen)
* [primgen] Instantiate tech libs in stable order (Philipp Wagner)
* [primgen] Actually find the Verible Python wrapper (Philipp Wagner)
* [dv/prim_esc] fix regression error (Cindy Chen)
* [dv/gpio] fix intr_test regression failure (Cindy Chen)
* [dv/common] Exclude assertion coverage from IP level testbench
  (Cindy Chen)
* [i2c, rtl] Update i2c.prj.hjson for D2 completion (Igor Kouznetsov)
* [dv/prince] hit additional toggle coverpoints (Udi Jonnalagadda)
* [sram_ctrl] Update docs (Michael Schaffner)
* [sram_ctrl] Absorb prim_ram_1p_scr (Michael Schaffner)
* [dv/gpio] Fix filter_stress test timeout (Cindy Chen)
* [dv/prim_alert/esc] Improvements for prim_alert/esc_tb (Cindy Chen)
* [dv/prim_esc] Direct test for prim_rx/tx (Cindy Chen)
* [dv/ips] Fix a few small items in gpio and hmac (Cindy Chen)
* [prim_xor2/lint] Add waiver for .* use in generated prim (Michael
  Schaffner)
* [dv, doc] Replace all 'dv.plan' with testplan (Srikrishna Iyer)
* [util, reggen] Support standardized cdc handling for regfile
  (Timothy Chen)
* [spi_host/dv] updated checkout list to track doc and testplan status
  (Rasmus Madsen)
* [spi_host/dv/doc] Updated dv plan for spi host for V1 review (Rasmus
  Madsen)
* [spi_host/dv/doc] Updated spi_host testplan (Rasmus Madsen)
* [i2c, doc] Checklist Update for D2 Sign-off (Igor Kouznetsov)
* [rtl/prim_alert_sender] Allow ping_req to stay high without error
  (Cindy Chen)
* [dv/prim_alert] Add a testbench for prim_alert (Cindy Chen)
* [prim_subreg_shadow] Make local parameter a localparam (Philipp
  Wagner)
* [prim_subreg] Make software access type an enum (Philipp Wagner)
* [rtl/prim_diff_decode] Add prim_flop_2sync dependency (Cindy Chen)
* [edn] Add MaxLatency assertion (Eunchan Kim)
* [prim_subreg_shadow] Correct write data signal usage (Michael
  Schaffner)
* [prim_lfsr] Fix assertion issue occuring right after reset (Michael
  Schaffner)
* [memutil] Allow use without scrambled memories (Philipp Wagner)
* [prim_prince] Fix comment (Philipp Wagner)
* [memutil] Fix width mismatch (Philipp Wagner)
* [prim] Allow disabling SVAs ensuring REQ is held until ACK at run
  time (Pirmin Vogel)
* [prim] Fix typo that caused fifo_async to get stuck (Timothy Chen)
* [prim] Add a missing ROM_CFG_DEFAULT to prim_rom_pkg.sv (Rupert
  Swarbrick)
* [prim_subreg_shadow] Invert meaning of SWACCESS in shadow/stage regs
  (Michael Schaffner)
* [prim_arb_tree/rv_plic_target] Remove TODOs due to a Vivado tool bug
  (Michael Schaffner)
* [primgen] Remove unused import (Philipp Wagner)
* [primgen] Add shebang (Philipp Wagner)
* [primgen] Make primgen "portable" again (Philipp Wagner)
* [rv_plic] rv_plic updates as part of rv_core_ibex templating
  (Timothy Chen)
* [ spi_host ] Fix Lint Errors (Martin Lueker-Boden)
* [fpv/rv_plic] Fix compile error with alert (Cindy Chen)
* [uart] Minor lint fix (Timothy Chen)
* [ spi_host ] Transition to D1 (Martin Lueker-Boden)
* [spi_host,doc] Update spi_host documentation (Martin Lueker-Boden)
* [pwm, dv] Fix fifo test for i2c host rtl (Tung Hoang)
* [dv/uart] Fix assertion (Weicai Yang)
* [doc/fpv] Unify the wording for IPs that verified in FPV (Cindy
  Chen)
* [reggen] Pair up clock and reset signals (Rupert Swarbrick)
* [integ alerts] Align description of integ alerts (Michael Schaffner)
* [tlul] Add some missing dependencies (Michael Schaffner)
* [rv_plic] Fix a bitwidth lint error (Michael Schaffner)
* [rv_plic] Wire up integ alert (Michael Schaffner)
* [otbn/otp_ctrl] Replicate dmem scrambling keystream (Michael
  Schaffner)
* [spi*/uart] Make sure integ alert is fatal (Michael Schaffner)
* [adc_ctrl] Various preparation steps for d2 (Timothy Chen)
* [dv/i2c] Fix alert clock/reset (Weicai Yang)
* [i2c, rtl] FIFO Depth Parameterization (Igor Kouznetsov)
* Revert "[prim] Do remove prim_esc.core from the dependencies"
  (Rupert Swarbrick)
* [prim] Remove dependency of prim:esc on a hardware block (Rupert
  Swarbrick)
* [lint] prim_ram_1p_scr verilator lint fixes (Greg Chadwick)
* [dv] Add scrambled_ecc32_mem_area for memutils (Greg Chadwick)
* [dv] Add C++ memory scrambling model (Greg Chadwick)
* [prim] Do remove prim_esc.core from the dependencies (Michael
  Schaffner)
* [i2c, doc] Updated Description of Clock Stretching by Target (Igor
  Kouznetsov)
* [reggen] Generate a single we/re signal per register in reg_top
  (Rupert Swarbrick)
* [alert_handler] Implement reverse ping feature (Michael Schaffner)
* [prim_esc] Split the prims into their own core file (Michael
  Schaffner)
* [uart/dv] Fix regression failure (Weicai Yang)
* [dv/common] Stress_all_with_rand_reset apply reset concurrently
  (Cindy Chen)
* [dv/all] update scoreboard `csr_addrs` accesses (Udi Jonnalagadda)
* [i2c, rtl] Lint fixes (Igor Kouznetsov)
* [reggen] Simplify reg_top ports if there's exactly one window
  (Rupert Swarbrick)
* [prim_fifo_async] Fix a width calculation issue in case of Depth = 1
  (Michael Schaffner)
* [dv] Add automated alert_test to all IPs with new tl_int alert
  (Cindy Chen)
* [i2c] Wire up integrity alert (Michael Schaffner)
* [uart/dv] reduce sim time for smoke test (Weicai Yang)
* [i2c, rtl] Lint Fixes (Igor Kouznetsov)
* [dv/stress_all_with_reset] Revert back IPs that uses apply_reset
  (Cindy Chen)
* [uart] Wire up integrity alert (Michael Schaffner)
* [gpio] Wire up bus integrity alert (Michael Schaffner)
* [i2c, dv] Fix csr_* and smoke test for I2C (Tung Hoang)
* [gpio/dv] add run-opt for gpio_tl_intg_err (Weicai Yang)
* [dv/edn_reset] Update IPs that overrides apply_reset task (Cindy
  Chen)
* [reggen] Make spacing uniform and simplify comments in reg_top
  (Rupert Swarbrick)
* [spi_host] Wire up integrity alert (Michael Schaffner)
* [uart/dv] Fix unmapped test (Weicai Yang)
* [prim_lfsr] Fix spyglass lint warnings (Michael Schaffner)
* [prim_alert*/prim_esc*] Rework placement of size_only bufs/flops
  (Michael Schaffner)
* [i2c, rtl] Fixes to Lint Errors and Changes to Clock Stretching by
  Target (Igor Kouznetsov)
* [doc, testplans] Fix non-existent tests (Srikrishna Iyer)
* [i2c, rtl] Loopback test and other changes (Igor Kouznetsov)
* [primgen] Use verible-verilog-syntax for parsing (Mariusz Glebocki)
* [rv_plic] fix Src width mismatch (Eunchan Kim)
* [prim] Break always_comb block to avoid apparent loop (Rupert
  Swarbrick)
* [fpv] update secded_gen (Cindy Chen)
* [dv/common] Improve coverage exclusion method (Cindy Chen)
* [dvsim] Testplanner refactor & covergroup support (Srikrishna Iyer)
* [otp_ctrl] Workaround for generated prim depending on generated prim
  (Michael Schaffner)
* [checklists] Update all checklists for consistency (Srikrishna Iyer)
* [prim_secded] Add C reference models for Hsiao encode (Greg
  Chadwick)
* [rtl/prim_async_fifo] Fix async fifo typo when depth <= 2 (Cindy
  Chen)
* [pads] - added AnalogIn1 pads for OTP supply (Arnon Sharlin)
* [dv/common] add ECC support to mem_bkdr_if (Udi Jonnalagadda)
* [prim_secded] Use _i/_o suffix for port names (Philipp Wagner)
* [prim_fifo_async] Style fixes (Philipp Wagner)
* [uart] Fix line continuation in DV code (Philipp Wagner)
* Remove non-ASCII characters from SV code and meson.build (Rupert
  Swarbrick)
* [ spi_host ] Remove cmd_len_q register to clean up DC logs (Martin
  Lueker-Boden)
* [fpv/spi_host] Fix undecleared variable issue (Cindy Chen)
* [ spi_device, spi_host, top_earlgrey ] Add SPI passthrough to
  spi_host (Martin Lueker-Boden)
* [uart,lint] Waive warning about unused field in uart reg2hw (Rupert
  Swarbrick)
* [ prim ] Suppress unneeded assertion when clearing prim_packer_fifo
  (Martin Lueker-Boden)
* [spi_host] Proper routing of sd_o in standard mode. (Martin Lueker-
  Boden)
* [all] Minor lint fixes (Timothy Chen)
* [regtool] Reformulate wr_err calculation to avoid long lines (Rupert
  Swarbrick)
* [prim_clock_div] Update waiver (Michael Schaffner)
* [prim] Make SECDED prim generation deterministic (Rupert Swarbrick)
* [prim_pad_attr/prim_flop_en] Add waiver files (Michael Schaffner)
* [spi_host] Minor lint fixes (Michael Schaffner)
* [prim_clock_div] Update waiver file (Michael Schaffner)
* [top] change prim_generic usage into prim (Timothy Chen)
* Add formatting changes from allow list (Rafal Kapuscik)
* [prim] Add generic and Xilinx-specific xor2 primitives (Pirmin
  Vogel)
* [prim] Add generic and Xilinx-specific enable-FF primitives (Pirmin
  Vogel)
* [ spi_host ] SPI_HOST Implementation (Martin Lueker-Boden)
* [pinmux/padring] Wire up the pad attribute WARL behavior modules
  (Michael Schaffner)
* [pad_wrapper] Extend the generic and Xilinx pad wrapper models
  (Michael Schaffner)
* [dv] Update scb for all blocks (Weicai Yang)
* [prim_arbiter,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [rv_plic,lint] Tell Verilator to split variables for scheduling
  (Rupert Swarbrick)
* [prim] Fix lint warnings, replace inline AscentLint waivers (Pirmin
  Vogel)
* [dv] Update `process_tl_access` args for all blocks (Weicai Yang)
* [formal] Clean up some formal warnings (Cindy Chen)
* [topgen] Rework pinmux datastructure and templatize tops (Michael
  Schaffner)
* [prim_fifo_async] Make async FIFO output zero when empty (Noah
  Moroze)
* [ci] Switch from a blacklist to a whitelist for executable files
  (Rupert Swarbrick)

Signed-off-by: Paul Scheffler <paulsc@iis.ee.ethz.ch>

* vendor: Re-patch opentitan peripherals

* vendor: Fixes to opentitan SPI

* vendor: Add SV APB UART

* vendor: Patch SV APB UART

* occamy: Integrate 16550-compliant APB UART, regenerate PLIC

* vendor: Update patches

vendor: Update SPI patches

* occamy: Fix SoC control overlay RTL issue

* fpga: Replace Xilinx UART with internal one

* Remove the Xilinx UART from the Block Design
* Map internal UART to UART0 of VCU128
* Update device tree
* Update ZSBL

Signed-off-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>

Co-authored-by: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
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