platform/ev3: Integrate am18x-lib.

.vscode/c_cpp_properties.json

@@ -67,6 +67,9 @@
                 "${workspaceFolder}/bricks/ev3",
                 "${workspaceFolder}/bricks/ev3/build",
                 "${workspaceFolder}/micropython",
+                "${workspaceFolder}/lib/am18x-lib/inc",
+                "${workspaceFolder}/lib/am18x-lib/lib",
+                "${workspaceFolder}/lib/am18x-lib/prj",
             ],
             "defines": [
                 "MICROPY_MODULE_FROZEN_MPY",

bricks/_common/arm_none_eabi.mk

@@ -130,6 +130,11 @@ endif
 ifeq ($(PB_LIB_STM32_USB_DEVICE),1)
 INC += -I$(PBTOP)/lib/STM32_USB_Device_Library/Core/Inc/
 endif
+ifeq ($(PB_MCU_FAMILY),TIAM1808)
+INC += -I$(PBTOP)/lib/am18x-lib/inc
+INC += -I$(PBTOP)/lib/am18x-lib/lib
+INC += -I$(PBTOP)/lib/am18x-lib/prj
+endif
 INC += -I$(PBTOP)
 INC += -I$(BUILD)
 
@@ -153,7 +158,7 @@ ifeq ($(PB_MCU_FAMILY),AT91SAM7)
 CFLAGS_MCU = -mthumb -mthumb-interwork -mtune=arm7tdmi -mcpu=arm7tdmi -msoft-float
 else
 ifeq ($(PB_MCU_FAMILY),TIAM1808)
-CFLAGS_MCU =
+CFLAGS_MCU = -mcpu=arm926ej-s -mabi=aapcs -gdwarf-2
 else
 $(error unsupported PB_MCU_FAMILY)
 endif
@@ -260,6 +265,58 @@ PY_EXTRA_SRC_C += $(addprefix bricks/ev3/,\
 SRC_S += shared/runtime/gchelper_thumb1.s
 endif
 
+# AM18X-LIB
+
+AM18X_LIB_PRJ_SRC_C = $(addprefix lib/am18x-lib/prj/,\
+	am1808exp.c \
+	am18x_conf.c \
+	tca6416.c \
+	tps6507x.c \
+	)
+
+AM18X_LIB_SRC_SRC_C = $(addprefix lib/am18x-lib/src/,\
+    am18x_aintc.c \
+    am18x_ddr.c \
+    am18x_edma.c \
+    am18x_i2c.c \
+    am18x_mmcsd.c \
+    am18x_pru.c \
+    am18x_rtc.c \
+    am18x_timer.c \
+    am18x_usb0.c \
+    am18x_dclk.c \
+    am18x_ecap.c \
+    am18x_gpio.c \
+    am18x_lcd.c \
+    am18x_pll.c \
+    am18x_psc.c \
+    am18x_syscfg.c \
+    am18x_uart.c \
+	)
+
+AM18X_LIB_LIB_SRC_C = $(addprefix lib/am18x-lib/lib/,\
+    arm920t.c \
+    ctype.c \
+    dvfs.c \
+    i2c_inf.c \
+    systick.c \
+    uart.c \
+	)
+
+AM18X_LIB_PRJ_SRC_S = $(addprefix lib/am18x-lib/prj/,\
+	abt_handler.S \
+	start.S \
+    uart_dbg.S \
+    undef_handler.S \
+	)
+
+AM18X_LIB_LIB_SRC_S = $(addprefix lib/am18x-lib/lib/,\
+    arm920t_s.S \
+    div64.S \
+    lib1funcs.S \
+    lshrdi3.S \
+	)
+
 # STM32 Bluetooth stack
 
 BLUENRG_SRC_C = $(addprefix lib/BlueNRG-MS/hci/,\
@@ -474,6 +531,21 @@ OBJ += $(addprefix $(BUILD)/, $(NXOS_SRC_C:.c=.o))
 OBJ += $(addprefix $(BUILD)/, $(NXOS_SRC_S:.s=.o))
 endif
 
+ifeq ($(PB_MCU_FAMILY),TIAM1808)
+OBJ += $(addprefix $(BUILD)/, $(AM18X_LIB_PRJ_SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(AM18X_LIB_SRC_SRC_C:.c=.o))
+OBJ += $(addprefix $(BUILD)/, $(AM18X_LIB_LIB_SRC_C:.c=.o))
+$(addprefix $(BUILD)/, $(AM18X_LIB_PRJ_SRC_C:.c=.o)): CFLAGS += -Wno-error=format= -Wno-format
+$(addprefix $(BUILD)/, $(AM18X_LIB_SRC_SRC_C:.c=.o)): CFLAGS += -Wno-error=format= -Wno-format
+$(addprefix $(BUILD)/, $(AM18X_LIB_LIB_SRC_C:.c=.o)): CFLAGS += -Wno-error=format= -Wno-format
+
+OBJ += $(addprefix $(BUILD)/, $(AM18X_LIB_PRJ_SRC_S:.S=.o))
+OBJ += $(addprefix $(BUILD)/, $(AM18X_LIB_LIB_SRC_S:.S=.o))
+$(addprefix $(BUILD)/, $(AM18X_LIB_PRJ_SRC_S:.S=.o)): CFLAGS += -D__ASSEMBLY__
+$(addprefix $(BUILD)/, $(AM18X_LIB_LIB_SRC_S:.S=.o)): CFLAGS += -D__ASSEMBLY__
+
+endif
+
 # List of sources for qstr extraction
 SRC_QSTR += $(PY_EXTRA_SRC_C) $(PYBRICKS_PYBRICKS_SRC_C)
 # Append any auto-generated sources that are needed by sources listed in SRC_QSTR

bricks/ev3/mpconfigport.h

@@ -78,14 +78,14 @@ typedef long mp_off_t;
 // value from disable_irq back to enable_irq.  If you really need
 // to know the machine-specific values, see irq.h.
 
+#include <arm920t.h>
+
 static inline void enable_irq(mp_uint_t state) {
-    // __set_PRIMASK(state);
+    arm_intr_enable();
 }
 
 static inline mp_uint_t disable_irq(void) {
-    // mp_uint_t state = __get_PRIMASK();
-    // __disable_irq();
-    // return state;
+    arm_intr_disable();
     return 0;
 }
 

bricks/ev3/mphalport.c

@@ -16,6 +16,10 @@
 #include "py/mpconfig.h"
 #include "py/stream.h"
 
+#include <systick.h>
+#include <arm920t.h>
+#include <am18x_aintc.h>
+
 void pb_stack_get_info(char **sstack, char **estack) {
 
     volatile int stack_dummy;
@@ -31,24 +35,17 @@ void pb_event_poll_hook_leave(void) {
     // have a critical section where we disable interrupts and check see if there
     // are any last second events. If not, we can call __WFI(), which still wakes
     // up the CPU on interrupt even though interrupts are otherwise disabled.
-
-
-    // TODO: TIAM1808 Implement commented out parts
-
-    // mp_uint_t state = disable_irq();
+    arm_intr_disable();
     if (!process_nevents()) {
-        // __WFI();
+        arm_wfi();
     }
-    // enable_irq(state);
+    arm_intr_enable();
 }
 
 // Core delay function that does an efficient sleep and may switch thread context.
 // If IRQs are enabled then we must have the GIL.
 void mp_hal_delay_ms(mp_uint_t Delay) {
-
-    // TODO: TIAM1808 implement IRQ enabled check
-
-    if (/*__get_PRIMASK() == 0*/ 0) {
+    if (aintc_get_active() != AINTC_INVALID_ACTIVE) {
         // IRQs enabled, so can use systick counter to do the delay
         uint32_t start = pbdrv_clock_get_ms();
         // Wraparound of tick is taken care of by 2's complement arithmetic.
@@ -60,7 +57,7 @@ void mp_hal_delay_ms(mp_uint_t Delay) {
         } while (pbdrv_clock_get_ms() - start < Delay);
     } else {
         // IRQs disabled, so need to use a busy loop for the delay.
-        // TODO: TIAM1808
+        systick_sleep(Delay);
     }
 }
 
@@ -80,7 +77,7 @@ typedef struct {
 } pb_hal_uart_t;
 
 // Sensor port 1
-static pb_hal_uart_t UART0 = { .thr = (volatile uint8_t *)0x01D0C000, .lsr = (volatile uint8_t *)0x01D0C014 };
+static pb_hal_uart_t DBG_UART = { .thr = (volatile uint8_t *)0x01D0C000, .lsr = (volatile uint8_t *)0x01D0C014 };
 
 static void debug(pb_hal_uart_t *uart, const char *s) {
     while (*s) {
@@ -91,7 +88,7 @@ static void debug(pb_hal_uart_t *uart, const char *s) {
 }
 
 void mp_hal_stdout_tx_strn(const char *str, mp_uint_t len) {
-    debug(&UART0, str);
+    debug(&DBG_UART, str);
     // MICROPY_EVENT_POLL_HOOK
 }
 

lib/am18x-lib/LICENSE.txt

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2013 - turmary@126.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

lib/am18x-lib/inc/am18x_aintc.h

@@ -0,0 +1,30 @@
+// tary, 0:01 2013/3/9
+
+#ifndef __AM18X_AINTC_H__
+#define __AM18X_AINTC_H__
+
+#include "am18x_map.h"
+
+typedef enum {
+	AINTC_GLOBAL,
+	AINTC_HOST_FIQ,
+	AINTC_HOST_IRQ,
+} aintc_host_t;
+
+typedef struct {
+	uint32_t	isr_addr;
+	uint32_t	isr_size;
+} aintc_conf_t;
+
+#define AINTC_INVALID_ACTIVE		(-1)
+
+am18x_rt aintc_conf(const aintc_conf_t* conf);
+am18x_rt aintc_enable(aintc_host_t host);
+am18x_rt aintc_disable(aintc_host_t host);
+am18x_rt aintc_sys_enable(AINTC_assign_t assign);
+am18x_rt aintc_sys_disable(AINTC_assign_t assign);
+am18x_rt aintc_trigger(AINTC_assign_t assign);
+am18x_rt aintc_clear(AINTC_assign_t assign);
+int32_t	 aintc_get_active(void);
+
+#endif//__AM18X_AINTC_H__

lib/am18x-lib/inc/am18x_dclk.h

@@ -0,0 +1,134 @@
+// tary, 19:03 2013/4/20
+
+#ifndef __AM18X_DCLK_H__
+#define __AM18X_DCLK_H__
+
+#include "am18x_map.h"
+
+typedef enum {
+	CLK_NODE_INVALID,
+
+	CLK_NODE_PLL0_SYSCLK1,
+	CLK_NODE_PLL0_SYSCLK2,
+	CLK_NODE_PLL0_SYSCLK3,
+	CLK_NODE_PLL0_SYSCLK4,
+	CLK_NODE_PLL0_SYSCLK5,
+	CLK_NODE_PLL0_SYSCLK6,
+	CLK_NODE_PLL0_SYSCLK7,
+	CLK_NODE_EMA_CLKSRC,
+	CLK_NODE_PLL0_AUXCLK,
+	CLK_NODE_PLL0_OBSCLK,
+	CLK_NODE_PLL1_SYSCLK1,
+	CLK_NODE_PLL1_SYSCLK2,
+	CLK_NODE_PLL1_SYSCLK3,
+	CLK_NODE_PLL1_OBSCLK,
+
+	CLK_NODE_ASYNC3,
+
+	CLK_NODE_PLL0_PLLEN,
+	CLK_NODE_PLL_EXTSRC,
+	CLK_NODE_POSTDIV0,
+	CLK_NODE_PLLM0,
+	CLK_NODE_PREDIV0,
+	CLK_NODE_PLL_CLKMODE,
+
+	CLK_NODE_DIV4_5X,
+	CLK_NODE_DIV4_5,
+
+	CLK_NODE_OSCDIV0,
+	CLK_NODE_OCSEL0_OCSRC,
+
+	CLK_NODE_PLL1_PLLEN,
+	CLK_NODE_POSTDIV1,
+	CLK_NODE_PLLM1,
+
+	CLK_NODE_OSCDIV1,
+	CLK_NODE_OCSEL1_OCSRC,
+
+	CLK_NODE_OSCIN,
+	CLK_NODE_CNT,
+} clk_node_id_t;
+
+typedef uint32_t (*pll_calc_freq_t) (uint32_t parent);
+
+typedef struct {
+	cuint32_t	id;
+	const char*	name;
+	uint32_t	parent;
+#define CN_FLAG_DIV			0x00000001UL
+#define CN_FLAG_MULT			0x00000002UL
+#define CN_FLAG_MULTI_DIV		0x00000003UL
+#define CN_FLAG_MUX			0x00000004UL
+#define CN_FLAG_REREAD			0x00000008UL
+#define CN_FLAG_RECALC			0x00000010UL
+#define CN_FLAG_VISITED			0x00000020UL
+	uint32_t	flag;
+	uint32_t	multiplier;
+	uint32_t	divider;
+	pll_calc_freq_t	calc_freq;
+	pll_calc_freq_t do_change;
+	uint32_t*	parent_list;
+	uint32_t	freq;
+} clk_node_t;
+
+#define DCLK_ID_GRP_SZ			0x100
+typedef enum {
+	DCLK_ID_ARM_RAM_ROM = CLK_NODE_PLL0_SYSCLK2 * DCLK_ID_GRP_SZ,
+	DCLK_ID_ON_CHIP_RAM,
+	DCLK_ID_UART0,
+	DCLK_ID_EDMA,
+	DCLK_ID_SPI0,
+	DCLK_ID_MMC_SDS,
+	DCLK_ID_VPIF,
+	DCLK_ID_LCDC,
+	DCLK_ID_SATA,
+	DCLK_ID_UPP,
+	DCLK_ID_DDR2_MDDR,
+	DCLK_ID_USB2_0,
+	DCLK_ID_HPI,
+	DCLK_ID_PRUSS,
+
+	DCLK_ID_EMIFA = CLK_NODE_EMA_CLKSRC * DCLK_ID_GRP_SZ,
+
+	DCLK_ID_SYSCFG = CLK_NODE_PLL0_SYSCLK4 * DCLK_ID_GRP_SZ,
+	DCLK_ID_GPIO,
+	DCLK_ID_PLLCS,
+	DCLK_ID_PSCS,
+	DCLK_ID_I2C1,
+	DCLK_ID_EMAC_MDIO,
+	DCLK_ID_USB1_1,
+	DCLK_ID_ARM_INTC,
+
+	DCLK_ID_ARM = CLK_NODE_PLL0_SYSCLK6 * DCLK_ID_GRP_SZ,
+
+	DCLK_ID_EMAC_RMII = CLK_NODE_PLL0_SYSCLK7 * DCLK_ID_GRP_SZ,
+
+	DCLK_ID_I2C0 = CLK_NODE_PLL0_AUXCLK * DCLK_ID_GRP_SZ,
+	DCLK_ID_TIMER64P0,
+	DCLK_ID_TIMER64P1,
+	DCLK_ID_RTC,
+	DCLK_ID_USB2_0_PHY,
+	DCLK_ID_MCASP0_SCLK,
+
+	DCLK_ID_DDR2_MDDR_PHY = CLK_NODE_PLL1_SYSCLK1 * DCLK_ID_GRP_SZ,
+
+	DCLK_ID_ECAPS = CLK_NODE_ASYNC3 * DCLK_ID_GRP_SZ,
+	DCLK_ID_UART1,
+	DCLK_ID_UART2,
+	DCLK_ID_TIMER64P2,
+	DCLK_ID_TIMER64P3,
+	DCLK_ID_EHRPWMS,
+	DCLK_ID_MCBSPS,
+	DCLK_ID_MCASP0,
+	DCLK_ID_SPI1,
+} dev_clk_id_t;
+
+am18x_rt clk_node_init(void);
+am18x_rt clk_node_output(void);
+am18x_rt clk_node_tree(void);
+am18x_rt clk_node_recalc(void);
+uint32_t clk_node_get_freq(uint32_t id);
+am18x_rt clk_node_set_parent(uint32_t id, uint32_t parent);
+uint32_t dev_get_freq(uint32_t dclk_id);
+
+#endif//__AM18X_DCLK_H__