Improvements and refactoring in stdlib and verilog backend

• Add several new test utility components to stdlib
• Improve run_sim and run_vector_sim, refactor plugin options
• Refactor all the tests to use the improved test utility functions
• Add finalize_verilator to run_sim and vector sims
• Rework several parts of RTLIR to accelerate translation
• Drastically improved verilator import performance and compilation time
• Accelerated the dynamic compilation of ff_flip

Official pymtl3 3.0 release

Merge pull request #186 from pymtl/dev-3.0-release

official 3.0 release

0.6 release

bump version to 0.6, the last release before 3.0 official release

Some new features and a lot of refactoring

• Bug fixes
• Translatable constant-size slicing
• Throw deprecation errors for deprecated primitives
• Support connecting a constant struct to a signal
• Implement hypothesis strategy for bitstructs and improve bits strategy
• passes/ folder major refactoring
• Tick function refactoring. Add eval_combinational to top.

Improve waveform dumping, fix ast caching

• The vcd generation pass had some bugs and cannot handle some cases correctly. I took a pass to fix the bugs and refactored the code.
• Merge in Kaishuo's text-based waveform pass
• The ast caching caches the value it gets from the globals/closure but it really shouldn't do so because two instances of the same class can have different closure content based on the parameter. I changed ast caching to cache the variable name and look them up on a per-instance basis during elaboration.

fix graphviz import

0.5.1

fix graphviz import

update_ff, new @bitstruct, and bug fixes

0.5

bump version to 0.5