target/xtensa: add sample_controller core

The sample_controller core is a simple noMMU general purpose core, modern
analog of de212. It is used as a default core in the xtensa port of
Zephyr.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

target/xtensa/Makefile.objs

@@ -3,6 +3,7 @@ obj-y += core-dc232b.o
 obj-y += core-dc233c.o
 obj-y += core-de212.o
 obj-y += core-fsf.o
+obj-y += core-sample_controller.o
 obj-$(CONFIG_SOFTMMU) += monitor.o
 obj-y += xtensa-isa.o
 obj-y += translate.o op_helper.o helper.o cpu.o

target/xtensa/core-sample_controller.c

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018, Max Filippov, Open Source and Linux Lab.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of the Open Source and Linux Lab nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "exec/exec-all.h"
+#include "exec/gdbstub.h"
+#include "qemu-common.h"
+#include "qemu/host-utils.h"
+
+#include "core-sample_controller/core-isa.h"
+#include "overlay_tool.h"
+
+#define xtensa_modules xtensa_modules_sample_controller
+#include "core-sample_controller/xtensa-modules.c"
+
+static XtensaConfig sample_controller __attribute__((unused)) = {
+    .name = "sample_controller",
+    .gdb_regmap = {
+        .reg = {
+#include "core-sample_controller/gdb-config.c"
+        }
+    },
+    .isa_internal = &xtensa_modules,
+    .clock_freq_khz = 10000,
+    DEFAULT_SECTIONS
+};
+
+REGISTER_CORE(sample_controller)