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target-arm: Support multiple address spaces in page table walks
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If we have a secure address space, use it in page table walks:
when doing the physical accesses to read descriptors, make them
through the correct address space.

(The descriptor reads are the only direct physical accesses
made in target-arm/ for CPUs which might have TrustZone.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
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pm215 committed Jan 21, 2016
1 parent 0faea0c commit 5ce4ff6
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Showing 2 changed files with 15 additions and 2 deletions.
9 changes: 9 additions & 0 deletions target-arm/cpu.h
Original file line number Diff line number Diff line change
Expand Up @@ -2003,6 +2003,15 @@ static inline int arm_asidx_from_attrs(CPUState *cs, MemTxAttrs attrs)
{
return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
}

/* Return the AddressSpace to use for a memory access
* (which depends on whether the access is S or NS, and whether
* the board gave us a separate AddressSpace for S accesses).
*/
static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
{
return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
}
#endif

#endif
8 changes: 6 additions & 2 deletions target-arm/helper.c
Original file line number Diff line number Diff line change
Expand Up @@ -6273,13 +6273,15 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
MemTxAttrs attrs = {};
AddressSpace *as;

attrs.secure = is_secure;
as = arm_addressspace(cs, attrs);
addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
if (fi->s1ptw) {
return 0;
}
return address_space_ldl(cs->as, addr, attrs, NULL);
return address_space_ldl(as, addr, attrs, NULL);
}

static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
Expand All @@ -6289,13 +6291,15 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
MemTxAttrs attrs = {};
AddressSpace *as;

attrs.secure = is_secure;
as = arm_addressspace(cs, attrs);
addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
if (fi->s1ptw) {
return 0;
}
return address_space_ldq(cs->as, addr, attrs, NULL);
return address_space_ldq(as, addr, attrs, NULL);
}

static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
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