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During process(), if a digital input is high, do not update the IIRs.
Strictly speaking the correct implementation is to update the y (output) delay line with the unchanged previous output, but keep updating the x delay line with new input. This seems to be semantically best implemented by updating with a "unity-gain-feedback-iir" instead of the usual "active" one. As a first approximation to this, just not calling iir.update(..) is fine.
Would be nice to have the pin functionality configurable or at least not conflicting. I.e. not have code conflict between the use of DIN0 as ref input for timestamping and the use as a GPIO (to be read explicitly). I.e. be able to use either functionality for DIN0 in different binaries. Conveniently, the DI0/1 signals each are available on two pins. This is easy then.
This integrator hold flag should be and-ed with a flag integrator_hold_chA_dinB_en and or-ed with a flag integrator_hold_chA from the network-accessible settings.
During
process()
, if a digital input is high, do not update the IIRs.y
(output) delay line with the unchanged previous output, but keep updating thex
delay line with new input. This seems to be semantically best implemented by updating with a "unity-gain-feedback-iir" instead of the usual "active" one. As a first approximation to this, just not callingiir.update(..)
is fine.integrator_hold_chA_dinB_en
and or-ed with a flagintegrator_hold_chA
from the network-accessible settings.Note: DINs should have pulldowns. sinara-hw/Stabilizer#91
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