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Load symbols for Verilog-A defined devices is broken #321

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ra3xdh opened this issue Oct 14, 2023 · 2 comments
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Load symbols for Verilog-A defined devices is broken #321

ra3xdh opened this issue Oct 14, 2023 · 2 comments
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bug
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2.1.0

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@ra3xdh
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ra3xdh commented Oct 14, 2023

Project->Load Verilog-A module has no effect. No new symbol appears in "verilog-a devices" group. Probably it may be related to #283
@ra3xdh ra3xdh added the bug label Oct 14, 2023
@ra3xdh ra3xdh added this to the 2.0.1 milestone Oct 14, 2023
ra3xdh added a commit that referenced this issue Oct 15, 2023
@ra3xdh
Fixed symbol loading for Verilog-A devices #321
107865a
@ra3xdh
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ra3xdh commented Oct 15, 2023

I have added a fix for this on current branch. Closing as completed.

@ra3xdh ra3xdh closed this as completed Oct 15, 2023
@tomhajjar
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Is there some Verilog-A test projects you can post? I have a number of them for Qucs 0.0.19 but porting them over to Qucs-S is problematic.

@ra3xdh ra3xdh mentioned this issue Nov 11, 2023
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