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clean up some constants in cluster.c
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@rajkosto
rajkosto committed Dec 6, 2018
1 parent c6c0884 commit 7836d58
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Showing 4 changed files with 110 additions and 23 deletions.
62 changes: 39 additions & 23 deletions src/hwinit/cluster.c
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Original file line number Diff line number Diff line change
Expand Up @@ -28,19 +28,22 @@ void _cluster_enable_power()
{
u8 tmp = max77620_recv_byte(MAX77620_REG_AME_GPIO);
max77620_send_byte(MAX77620_REG_AME_GPIO, tmp & 0xDF);
max77620_send_byte(MAX77620_REG_GPIO5, 0x09);

//Enable cores power.
i2c_send_byte(I2C_5, 0x1B, 0x2, 0x20);
i2c_send_byte(I2C_5, 0x1B, 0x3, 0x8D);
i2c_send_byte(I2C_5, 0x1B, 0x0, 0xB7);
i2c_send_byte(I2C_5, 0x1B, 0x1, 0xB7);
max77620_send_byte(MAX77620_REG_GPIO5, MAX77620_CNFG_GPIO_DRV_PUSHPULL | MAX77620_CNFG_GPIO_OUTPUT_VAL_HIGH);

// Enable cores power.
max7762x_send_byte(MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL1_REG,
MAX77621_AD_ENABLE | MAX77621_NFSR_ENABLE | MAX77621_SNS_ENABLE); // 1-3.x: MAX77621_NFSR_ENABLE
max7762x_send_byte(MAX77621_CPU_I2C_ADDR, MAX77621_CONTROL2_REG,
MAX77621_T_JUNCTION_120 | MAX77621_WDTMR_ENABLE | MAX77621_CKKADV_TRIP_75mV_PER_US| MAX77621_INDUCTOR_NOMINAL);
// 1-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL
max7762x_send_byte(MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_REG, MAX77621_VOUT_ENABLE | 0x37);
max7762x_send_byte(MAX77621_CPU_I2C_ADDR, MAX77621_VOUT_DVC_REG, MAX77621_VOUT_ENABLE | 0x37);
}

int _cluster_pmc_enable_partition(u32 part, u32 toggle)
int _cluster_pmc_enable_partition(u32 part, u32 toggle, u32 enable)
{
//Check if the partition has already been turned on.
if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part)
if (enable && (PMC(APBDEV_PMC_PWRGATE_STATUS) & part))
return 1;

u32 startTime = get_tmr_ms();
Expand All @@ -50,7 +53,7 @@ int _cluster_pmc_enable_partition(u32 part, u32 toggle)
return 0;
}

PMC(APBDEV_PMC_PWRGATE_TOGGLE) = toggle | 0x100;
PMC(APBDEV_PMC_PWRGATE_TOGGLE) = toggle | (enable ? 0x100 : 0);

startTime = get_tmr_ms();
while ((PMC(APBDEV_PMC_PWRGATE_STATUS) & part) == 0)
Expand All @@ -62,23 +65,36 @@ int _cluster_pmc_enable_partition(u32 part, u32 toggle)
return 1;
}

#define PLLX_VALUE_FROM_DIVS(DIVM, DIVN, DIVP) (((DIVP & 0x1F) << 20) | ((DIVN & 0xFF) << 8) | (DIVM & 0xFF))

void cluster_boot_cpu0(u32 entry)
{
struct flow_ctlr* const flow = (void *)FLOW_CTLR_BASE;

//Set ACTIVE_CLUSER to FAST.
flow->cluster_control &= 0xFFFFFFFE;
struct flow_ctlr* const flow = (void *)FLOW_CTLR_BASE;
flow->bpmp_cluster_control &= ~(1u << 0); //Set ACTIVE_CLUSER to FAST.

_cluster_enable_power();

if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000))
//final_freq = ((38.4MHz / DIVM) * DIVN) / (2^DIVP)
typedef struct freqEntry_s { u32 clkFreqHz; u32 pllxDividers; } freqEntry_t;
static const freqEntry_t frequencies[] =
{
{ 93600000, PLLX_VALUE_FROM_DIVS(2, 78, 4) }, //93.6MHz (bench: 6677351 us)
{ 187200000, PLLX_VALUE_FROM_DIVS(2, 78, 3) }, //187.2MHz (bench: 5341881 us)
{ 249600000, PLLX_VALUE_FROM_DIVS(3, 156, 3) }, //249.6MHz (bench: 4006410 us)
{ 499200000, PLLX_VALUE_FROM_DIVS(3, 156, 2) }, //499.2MHz (bench: 3004808 us)
{ 748800000, PLLX_VALUE_FROM_DIVS(2, 78, 1) }, //748.8MHz (bench: 2670940 us)
{ 998400000, PLLX_VALUE_FROM_DIVS(3, 156, 1) } //998.4MHz (bench: 2003206 us)
};

static const u32 pllxDividers = frequencies[0].pllxDividers;
if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & (1u << 30)))
{
CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7;
CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= ~(1u << 3);
usleep(2);
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x00404E02;
CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) |= 0x40000;
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x40404E02;
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = (1u << 31) | pllxDividers;
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x00000000 | pllxDividers;
CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) |= (1u << 18);
CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = (1u << 30) | pllxDividers;
}
while (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x8000000)) {}

Expand All @@ -97,11 +113,11 @@ void cluster_boot_cpu0(u32 entry)
CLOCK(CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2) &= 0xFFFFF000;

//Enable CPU rail.
_cluster_pmc_enable_partition(1, 0);
_cluster_pmc_enable_partition(1, 0, 1);
//Enable cluster 0 non-CPU.
_cluster_pmc_enable_partition(0x8000, 15);
_cluster_pmc_enable_partition(0x8000, 15, 1);
//Enable CE0.
_cluster_pmc_enable_partition(0x4000, 14);
_cluster_pmc_enable_partition(0x4000, 14, 1);

//Request and wait for RAM repair.
flow->ram_repair = 1;
Expand Down
14 changes: 14 additions & 0 deletions src/hwinit/flow.h
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Original file line number Diff line number Diff line change
Expand Up @@ -41,6 +41,20 @@ struct flow_ctlr {
vu32 flow_ctlr_spare; /* offset 0x54 */
vu32 reserved; /* offset 0x58 */
vu32 fc_seq_intercept; /* offset 0x5c */
vu32 cc4_retention_control; /* offset 0x64 */
vu32 cc4_fc_status; /* offset 0x68 */
vu32 cc4_core0_ctrl; /* offset 0x6c */
vu32 cc4_core1_ctrl; /* offset 0x70 */
vu32 cc4_core2_ctrl; /* offset 0x74 */
vu32 cc4_core3_ctrl; /* offset 0x78 */
vu32 core0_idle_counter; /* offset 0x7c */
vu32 core1_idle_counter; /* offset 0x80 */
vu32 core2_idle_counter; /* offset 0x84 */
vu32 core3_idle_counter; /* offset 0x88 */
vu32 cc4_hvc_retry; /* offset 0x8c */
vu32 l2flush_timeout_cntr; /* offset 0x90 */
vu32 l2flush_control; /* offset 0x94 */
vu32 bpmp_cluster_control; /* offset 0x98 */
};

enum {
Expand Down
9 changes: 9 additions & 0 deletions src/hwinit/max7762x.c
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Original file line number Diff line number Diff line change
Expand Up @@ -70,6 +70,15 @@ u8 max77620_recv_byte(u32 regAddr)
return i2c_recv_byte(I2C_5, 0x3C, regAddr);
}

u32 max7762x_send_byte(u32 devAddr, u32 regAddr, u8 dataByte)
{
return i2c_send_byte(I2C_5, devAddr, regAddr, dataByte);
}
u8 max7762x_recv_byte(u32 devAddr, u32 regAddr)
{
return i2c_recv_byte(I2C_5, devAddr, regAddr);
}

int max77620_regulator_get_status(u32 id)
{
if (id > REGULATOR_MAX)
Expand Down
48 changes: 48 additions & 0 deletions src/hwinit/max7762x.h
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Original file line number Diff line number Diff line change
Expand Up @@ -59,9 +59,57 @@
#define REGULATOR_LDO8 12
#define REGULATOR_MAX 12

#define MAX77621_CPU_I2C_ADDR 0x1B
#define MAX77621_GPU_I2C_ADDR 0x1C

#define MAX77621_VOUT_REG 0
#define MAX77621_VOUT_DVC_REG 1
#define MAX77621_CONTROL1_REG 2
#define MAX77621_CONTROL2_REG 3

/* MAX77621_VOUT */
#define MAX77621_VOUT_ENABLE (1 << 7)
#define MAX77621_VOUT_MASK 0x7F

/* MAX77621_VOUT_DVC_DVS */
#define MAX77621_DVS_VOUT_MASK 0x7F

/* MAX77621_CONTROL1 */
#define MAX77621_SNS_ENABLE (1 << 7)
#define MAX77621_FPWM_EN_M (1 << 6)
#define MAX77621_NFSR_ENABLE (1 << 5)
#define MAX77621_AD_ENABLE (1 << 4)
#define MAX77621_BIAS_ENABLE (1 << 3)
#define MAX77621_FREQSHIFT_9PER (1 << 2)

#define MAX77621_RAMP_12mV_PER_US 0x0
#define MAX77621_RAMP_25mV_PER_US 0x1
#define MAX77621_RAMP_50mV_PER_US 0x2
#define MAX77621_RAMP_200mV_PER_US 0x3
#define MAX77621_RAMP_MASK 0x3

/* MAX77621_CONTROL2 */
#define MAX77621_WDTMR_ENABLE (1 << 6)
#define MAX77621_DISCH_ENBABLE (1 << 5)
#define MAX77621_FT_ENABLE (1 << 4)
#define MAX77621_T_JUNCTION_120 (1 << 7)

#define MAX77621_CKKADV_TRIP_DISABLE 0xC
#define MAX77621_CKKADV_TRIP_75mV_PER_US 0x0
#define MAX77621_CKKADV_TRIP_150mV_PER_US 0x4
#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS 0x8

#define MAX77621_INDUCTOR_MIN_30_PER 0x0
#define MAX77621_INDUCTOR_NOMINAL 0x1
#define MAX77621_INDUCTOR_PLUS_30_PER 0x2
#define MAX77621_INDUCTOR_PLUS_60_PER 0x3

u32 max77620_send_byte(u32 regAddr, u8 dataByte);
u8 max77620_recv_byte(u32 y);

u32 max7762x_send_byte(u32 devAddr, u32 regAddr, u8 dataByte);
u8 max7762x_recv_byte(u32 devAddr, u32 y);

int max77620_regulator_get_status(u32 id);
int max77620_regulator_config_fps(u32 id);
int max77620_regulator_set_voltage(u32 id, u32 mv);
Expand Down

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