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A pipelined implementation of the RISC-V-32I Processor with support for compressed instructions (Verilog)

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Tests		Tests
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RISCV-32I

A pipelined implementation of the RISC-V-32I Processor with support for compressed instructions. It was fully implemented in Verilog.

Contributers:

1-Ramez Moussa
2-Hany Moussa
3-Abdallah A. Elrefai
4-Mohamed A. Eltohfa

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A pipelined implementation of the RISC-V-32I Processor with support for compressed instructions (Verilog)

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