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trigger_mode == -1 (default) => no effect / no registers written
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trigger_mode == 1 => source
trigger_mode == 2 => sink

This can be set e.g. in /boot/cmdline.txt as imx477.trigger_mode=N

Tested on HQ cameras (XVS <-> XVS, GND <-> GND) with libcamera.

Signed-off-by: Jonas Jacob <jonas.jacob@neocortexvision.com>
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neocortex-vision committed Oct 28, 2021
1 parent b1d32a2 commit 67cc4b0
Showing 1 changed file with 6 additions and 6 deletions.
12 changes: 6 additions & 6 deletions drivers/media/i2c/imx477.c
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ static int dpc_enable = 1;
module_param(dpc_enable, int, 0644);
MODULE_PARM_DESC(dpc_enable, "Enable on-sensor DPC");

static int trigger_mode = 0;
static int trigger_mode = -1;
module_param(trigger_mode, int, 0644);
MODULE_PARM_DESC(trigger_mode, "Set vsync trigger mode: 1=source, 2=sink");

Expand Down Expand Up @@ -1730,18 +1730,18 @@ static int imx477_start_streaming(struct imx477 *imx477)
imx477_write_reg(imx477, 0x0b06, IMX477_REG_VALUE_08BIT, !!dpc_enable);

/* Set vsync trigger mode */
if (trigger_mode != 0) {
if (trigger_mode > 0) {
/* trigger_mode == 1 for source, 2 for sink */
const u32 val = (trigger_mode == 1) ? 1 : 0;

imx477_write_reg(imx477, IMX477_REG_MC_MODE,
IMX477_REG_VALUE_08BIT, 1);
IMX477_REG_VALUE_08BIT, 1);
imx477_write_reg(imx477, IMX477_REG_MS_SEL,
IMX477_REG_VALUE_08BIT, val);
IMX477_REG_VALUE_08BIT, val);
imx477_write_reg(imx477, IMX477_REG_XVS_IO_CTRL,
IMX477_REG_VALUE_08BIT, val);
IMX477_REG_VALUE_08BIT, val);
imx477_write_reg(imx477, IMX477_REG_EXTOUT_EN,
IMX477_REG_VALUE_08BIT, val);
IMX477_REG_VALUE_08BIT, val);
}

/* Apply customized values from user */
Expand Down

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